资源列表
[VHDL编程] digitalpaobiao
说明:用Verilog HDL语言编写的数字跑表源程序,已经通过综合编译及仿真。-With the Verilog HDL source code written in digital stopwatch has been through a comprehensive compilation and simulation.<匡匡> 在 2025-06-06 上传 | 大小:113kb | 下载:0
[VHDL编程] FPGA_FILTER
说明:利用FPGA设计降采样滤波器的方法,希望对你有用-FPGA design using down-sampling filter, and I hope useful to you<mengzi> 在 2025-06-06 上传 | 大小:113kb | 下载:0
[VHDL编程] subber
说明:完成一位二进制全减器的设计,采用原理图输入法和文本输入法分别实现,分层设计,底层由半加器(也用原理图输入法)和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the half adder (also used schematic<sxh> 在 2025-06-06 上传 | 大小:113kb | 下载:0
[VHDL编程] shuzidianlu
说明:基于fpga的数字电路可程设计,一个乒乓球游戏机。可以算人对打,5局三胜-Fpga based digital circuit design process, a table tennis game. Operators who can rally, winning three out of 5<付友> 在 2025-06-06 上传 | 大小:113kb | 下载:0
[VHDL编程] EXCD1yuanlitu
说明:EXCD-1 Spartan 3E开发板原理图-EXCD-1 Spartan 3E development board schematics<hhq> 在 2025-06-06 上传 | 大小:113kb | 下载:0