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[VHDL编程] digital_frequency
说明:用verilog实现数字频率计的设计,具有自动换挡功能,采用t法和m法设计,低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.<孙岩> 在 2025-06-10 上传 | 大小:481kb | 下载:0
[VHDL编程] spi_controller
说明:SPI控制器,基于VERILOG描述,分模块设计,共6个模块,时钟产生模块,移位模块,主模块,从模块,定义模块,顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top modul<Liuhuan> 在 2025-06-10 上传 | 大小:481kb | 下载:0
[VHDL编程] frequency divider and testbench
说明:a frequency divider and test bench with simulation results<abitofhero> 在 2025-06-10 上传 | 大小:482kb | 下载:0
[VHDL编程] 10_100m_ethernet-fifo_convertor
说明:10_100m_ethernet-fifo_convertor<二叠好> 在 2025-06-10 上传 | 大小:482kb | 下载:1