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[VHDL编程] alu
说明：This 8 bit unsigned arithematic logical unit(ALU). This code is developed in VHDL language and compatible with any VHDL softeware like xilinx,quartus. This ALU performs addition,subtraction,multiplication,and,or,and not and pass input functions.-<chunduru> 在 2025-06-26 上传 | 大小：92kb | 下载：0
[VHDL编程] Serpar
说明：A serial to parallel converter is somewhat the reverse of the operation of parallel to serial converter. The data comes serially from the input port SERIN. The parallel data is output from DOUT port. Output port DRDY is asserted ‘1’ when the start bi<riadh> 在 2025-06-26 上传 | 大小：1kb | 下载：0
[VHDL编程] QPSKmapping
说明：CODE OF QPSK:The mapping module used is QPSK type of modulation<riadh> 在 2025-06-26 上传 | 大小：1kb | 下载：0
[VHDL编程] chu_fpga_prototyping_using_verilog_examples_huyho
说明：interesting book about verilog and fpga with many useful example<ngocphukmt> 在 2025-06-26 上传 | 大小：16.32mb | 下载：0
[VHDL编程] verilog--beep_ambulance
说明：altera FPGA学习测试例程序 蜂鸣器演示救护车声音 verilog beep_ambulance-altera FPGA test case study demonstrates the ambulance program buzzer sounds verilog beep_ambulance<yangpu> 在 2025-06-26 上传 | 大小：294kb | 下载：1
[VHDL编程] fifo_verilog
说明：用verilog 实现 fifo，宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs<张小琛> 在 2025-06-26 上传 | 大小：4kb | 下载：0