资源列表
[VHDL编程] Altera_timing
说明:本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle<yeping> 在 2025-06-15 上传 | 大小:1.46mb | 下载:0
[VHDL编程] uart
说明:用FPGA实现uart的verilog源码,包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove<wangyu> 在 2025-06-15 上传 | 大小:2kb | 下载:0
[VHDL编程] spi_master_control
说明:VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website<lonely_vv> 在 2025-06-15 上传 | 大小:655kb | 下载:0
[VHDL编程] PS2_IP_CORE
说明:该IP核是一个ps2键盘的源代码(vhdl语言)-The IP core is a ps2 keyboard source code (vhdl language)<liushui> 在 2025-06-15 上传 | 大小:26kb | 下载:0
[VHDL编程] EDA_tel_counter
说明:在EDA教学试验箱上(忘了学校的试验箱型号了)实现电话计费器功能-EDA teaching in the chamber to achieve telephone billing function<lian> 在 2025-06-15 上传 | 大小:52kb | 下载:0
[VHDL编程] cronometro
说明:This the program of a timer with a accuracy of ms-This is the program of a timer with a accuracy of ms<Sergio> 在 2025-06-15 上传 | 大小:1.47mb | 下载:0
[VHDL编程] uart
说明:This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.<Balazs Jozsa> 在 2025-06-15 上传 | 大小:1kb | 下载:0