资源列表
[VHDL编程] qvgatiming
说明:QVGA的Timing verilog 描述-Timing verilog descr iption of QVGA<vico> 在 2025-06-09 上传 | 大小:1kb | 下载:0
[VHDL编程] white_rim_testbench
说明:QVGA显示白框的test bench程序-QVGA display white box test bench procedures<vico> 在 2025-06-09 上传 | 大小:1kb | 下载:0
[VHDL编程] Asynchronous_read_write_RAM
说明:Dual Port RAM Asynchronous Read/Write 经过modelsim仿真 -Dual Port RAM Asynchronous Read/Write through ModelSim Simulation<lianlianmao> 在 2025-06-09 上传 | 大小:1kb | 下载:0
[VHDL编程] Synchronous_read_write_RAM
说明:Synchronous read write RAM verilog。经过modelsim se仿真。-Synchronous read write RAM verilog. Through simulation modelsim se.<lianlianmao> 在 2025-06-09 上传 | 大小:1kb | 下载:0
[VHDL编程] Synthesizable_FIFO_verilog
说明:Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is<lianlianmao> 在 2025-06-09 上传 | 大小:16kb | 下载:0