[VHDL编程] CacheFromScratchFinalWeek_ise12migration

说明：VHDL implementation of an 8-bit multilevel cache. Produces timing diagrams when run on a suitable IDE such as Xilinx.
<Josh> 在 2025-06-15 上传 | 大小：803kb | 下载：0

[VHDL编程] VGA

说明：quartus ii verilog hdl 实现VGA时序及显示的工程和源程序 -quartus ii verilog hdl vga timing project and source code
<zhaoyulong> 在 2025-06-15 上传 | 大小：54kb | 下载：0

[VHDL编程] PCF8563

说明：quartus ii 实时时钟pcf8563工程及源码 Verilog hdl 实现iic总线-quartusii realtime pcf8563 project and code and IIC verilog hdl
<zhaoyulong> 在 2025-06-15 上传 | 大小：73kb | 下载：0

[VHDL编程] I2C_contrl_LED

说明：I2C的top文件，是按照标准的I2C协议编写的，已通过调试，放心使用-I2C s top document is written in accordance with standard I2C protocol has been through debugging, ease of use
<张猛> 在 2025-06-15 上传 | 大小：9kb | 下载：0

[VHDL编程] sync_fifo

说明：同步fifo实现代码，包括的参数：数据宽度、fifo深度、地址宽度；状态信息包括：full, empty。-verilog RTL code which implement a synchronous FIFO function with data width, fifo depth, address pointer width parameterized.
<BaiLi> 在 2025-06-15 上传 | 大小：1kb | 下载：0

[VHDL编程] license_ISE_11_to_12_AVNET-yyy

说明：ise11.1的license，包括了fifo等IP核，谢谢大家的光顾。-ise11.1‘s license which provided some ip like fifo.
<yyy> 在 2025-06-15 上传 | 大小：467kb | 下载：0

[VHDL编程] top

说明：FPGA开发UART软件有一定的参考价值，请参考该软件进行编译Altera软件编写的-FPGA development software UART has some reference value, refer to the software to compile software written Altera
<whq> 在 2025-06-15 上传 | 大小：2.63mb | 下载：0

[VHDL编程] lpf

说明：利用altera的IP核构建的并行数字滤波器，实现100kHZ低通，带外抑制40dB-Altera use IP cores constructed parallel digital filters achieve 100kHZ low pass, band rejection of 40dB
<周正坤> 在 2025-06-15 上传 | 大小：13.03mb | 下载：0

[VHDL编程] uart_ram

说明：串口接收数据校样后存入双口ram,接收完整帧数据后，置中断，通知串口发送-After receiving proof serial data stored in dual port ram, receive a complete fr a me of data after the interrupt, serial port to send notifications
<yxs> 在 2025-06-15 上传 | 大小：4.17mb | 下载：0

[VHDL编程] ieep1.3

说明：10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces th
<john> 在 2025-06-15 上传 | 大小：495kb | 下载：0

[VHDL编程] ieep1.4

说明：10-b binary-weighted D/A converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-pm double-metal CMOS technology and the chip are
<john> 在 2025-06-15 上传 | 大小：488kb | 下载：0

[VHDL编程] ieep1.5

说明：This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-pm double-poly double-metal CMOS technology. In the DAC, a new current source called the thresholdvoltage compensated current source is used in the two-stage current array to r
<john> 在 2025-06-15 上传 | 大小：578kb | 下载：0