文件名称:traffic_controller
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 34kb
- 下载次数：
- 0次
- 提 供 者：
- yasir******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.
相关搜索： verilog
Traffic
light
ise
traffic
light
controller
verilog
code
traffic
light
traffic
light
verilog
Traffic
Light
Controller
Verilog
machine
TRAFFIC
LIGHT
CONTROLLER
VHDL
相关搜索： verilog
Traffic
light
ise
traffic
light
controller
verilog
code
traffic
light
traffic
light
verilog
Traffic
Light
Controller
Verilog
machine
TRAFFIC
LIGHT
CONTROLLER
VHDL
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下载文件列表
traffic_controller
..................\bench
..................\.....\tb_traffic_controller.v
..................\doc
..................\rtl
..................\...\cnter_enb_ovf.v
..................\...\traffic_controller.v
..................\...\traffic_sm.v
..................\sim
..................\...\History
..................\...\traffic_controller.cr.mti
..................\...\traffic_controller.mpf
..................\...\vsim.wlf
..................\...\wave.do
..................\...\work
..................\...\....\cnter_enb_ovf
..................\...\....\.............\verilog.asm
..................\...\....\.............\_primary.dat
..................\...\....\.............\_primary.vhd
..................\...\....\tb_traffic_controller
..................\...\....\.....................\fast.asm
..................\...\....\.....................\verilog.asm
..................\...\....\.....................\_primary.dat
..................\...\....\.....................\_primary.vhd
..................\...\....\traffic_controller
..................\...\....\..................\verilog.asm
..................\...\....\..................\_primary.dat
..................\...\....\..................\_primary.vhd
..................\...\....\traffic_sm
..................\...\....\..........\verilog.asm
..................\...\....\..........\_primary.dat
..................\...\....\..........\_primary.vhd
..................\...\....\_info
..................\bench
..................\.....\tb_traffic_controller.v
..................\doc
..................\rtl
..................\...\cnter_enb_ovf.v
..................\...\traffic_controller.v
..................\...\traffic_sm.v
..................\sim
..................\...\History
..................\...\traffic_controller.cr.mti
..................\...\traffic_controller.mpf
..................\...\vsim.wlf
..................\...\wave.do
..................\...\work
..................\...\....\cnter_enb_ovf
..................\...\....\.............\verilog.asm
..................\...\....\.............\_primary.dat
..................\...\....\.............\_primary.vhd
..................\...\....\tb_traffic_controller
..................\...\....\.....................\fast.asm
..................\...\....\.....................\verilog.asm
..................\...\....\.....................\_primary.dat
..................\...\....\.....................\_primary.vhd
..................\...\....\traffic_controller
..................\...\....\..................\verilog.asm
..................\...\....\..................\_primary.dat
..................\...\....\..................\_primary.vhd
..................\...\....\traffic_sm
..................\...\....\..........\verilog.asm
..................\...\....\..........\_primary.dat
..................\...\....\..........\_primary.vhd
..................\...\....\_info