文件名称:serial
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-- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是
--9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
--划分为8个时隙以使通信同步.
--程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome"
--字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制
--数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A相关搜索： VHDL
涓插彛
VHDL
串口
串口
vhdl
数码管
时隙
cpld
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是
--9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
--划分为8个时隙以使通信同步.
--程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome"
--字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制
--数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A相关搜索： VHDL
涓插彛
VHDL
串口
串口
vhdl
数码管
时隙
cpld
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下载文件列表
serial
......\Block1.bdf
......\serial.asm.rpt
......\serial.bdf
......\serial.bsf
......\serial.cdf
......\serial.done
......\serial.fit.eqn
......\serial.fit.rpt
......\serial.fit.smsg
......\serial.fit.summary
......\serial.flow.rpt
......\serial.map.eqn
......\serial.map.rpt
......\serial.map.summary
......\serial.pin
......\serial.pof
......\serial.qpf
......\serial.qsf
......\serial.qws
......\serial.sof
......\serial.tan.rpt
......\serial.tan.summary
......\serial_assignment_defaults.qdf
......\serial_test.bsf
......\serial_test.vhd
......\serial_test.vhd.bak
......\setup.tcl
......\setup.tcl.bak
......\Block1.bdf
......\serial.asm.rpt
......\serial.bdf
......\serial.bsf
......\serial.cdf
......\serial.done
......\serial.fit.eqn
......\serial.fit.rpt
......\serial.fit.smsg
......\serial.fit.summary
......\serial.flow.rpt
......\serial.map.eqn
......\serial.map.rpt
......\serial.map.summary
......\serial.pin
......\serial.pof
......\serial.qpf
......\serial.qsf
......\serial.qws
......\serial.sof
......\serial.tan.rpt
......\serial.tan.summary
......\serial_assignment_defaults.qdf
......\serial_test.bsf
......\serial_test.vhd
......\serial_test.vhd.bak
......\setup.tcl
......\setup.tcl.bak