文件名称:SDRAM_VerilogCode
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基于FPGA的SDRAM控制器Verilog代码，开发环境为Quartus6.1，控制SDRAM实现对同一片地址先写后读。-FPGA-based SDRAM controller Verilog code, development environment for Quartus6.1, control of SDRAM to achieve the same address one after the first time to write.相关搜索： SDRAM
controller
verilog
SDR
SDRAM
MT48LC16M16A2
controller
controller
verilog
SDR
SDRAM
MT48LC16M16A2
controller
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下载文件列表
SDRAM Verilog代码及测试程序
...........................\CVS
...........................\...\Entries
...........................\...\Repository
...........................\...\Root
...........................\rtl
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\transcript
...........................\...\yadmc.v
...........................\...\yadmc_dpram.v
...........................\...\yadmc_sdram16.v
...........................\...\yadmc_spram.v
...........................\...\yadmc_sync.v
...........................\test
...........................\....\CVS
...........................\....\...\Entries
...........................\....\...\Repository
...........................\....\...\Root
...........................\....\mt48lc16m16a2.v
...........................\....\mt48lc16m16a2_modeltb.v
...........................\....\runsim.sh
...........................\....\transcript
...........................\....\yadmc_test.v
...........................\yadmc_block.dia
...........................\CVS
...........................\...\Entries
...........................\...\Repository
...........................\...\Root
...........................\rtl
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\transcript
...........................\...\yadmc.v
...........................\...\yadmc_dpram.v
...........................\...\yadmc_sdram16.v
...........................\...\yadmc_spram.v
...........................\...\yadmc_sync.v
...........................\test
...........................\....\CVS
...........................\....\...\Entries
...........................\....\...\Repository
...........................\....\...\Root
...........................\....\mt48lc16m16a2.v
...........................\....\mt48lc16m16a2_modeltb.v
...........................\....\runsim.sh
...........................\....\transcript
...........................\....\yadmc_test.v
...........................\yadmc_block.dia