文件名称:aescore
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基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
相关搜索： VHDL
code
of
AES
AES
verilog
op
aes
verilog
code
aes
Verilog
AES
in
VHDL
Verilog
AES
AES
based
algorithm
相关搜索： VHDL
code
of
AES
AES
verilog
op
aes
verilog
code
aes
Verilog
AES
in
VHDL
Verilog
AES
AES
based
algorithm
(系统自动生成,下载前可以参看下载内容)
下载文件列表
aes core\aes.pdf
........\..._core\bench\verilog\test_bench_top.v
........\........\doc\aes.pdf
........\........\rtl\verilog\aes_cipher_top.v
........\........\...\.......\aes_inv_cipher_top.v
........\........\...\.......\aes_inv_sbox.v
........\........\...\.......\aes_key_expand_128.v
........\........\...\.......\aes_rcon.v
........\........\...\.......\aes_sbox.v
........\........\...\.......\timescale.v
........\........\...\.......\transcript
........\........\sim\rtl_sim\bin\Makefile
........\........\...\.......\run\waves\waves.do
........\........\.yn\bin\comp.dc
........\........\...\...\design_spec.dc
........\........\...\...\lib_spec.dc
........\........\...\...\read.dc
........\........\vim_session.vim
........\aes_core.tar.gz
........\OPENCORES.files\dotty.gif
........\...............\title_logo.gif
........\OPENCORES.htm
........\aes_core\sim\rtl_sim\run\waves
........\........\...\.......\bin
........\........\...\.......\run
........\........\bench\verilog
........\........\rtl\verilog
........\........\sim\rtl_sim
........\........\.yn\bin
........\........\bench
........\........\doc
........\........\rtl
........\........\sim
........\........\syn
........\aes_core
........\OPENCORES.files
aes core
........\..._core\bench\verilog\test_bench_top.v
........\........\doc\aes.pdf
........\........\rtl\verilog\aes_cipher_top.v
........\........\...\.......\aes_inv_cipher_top.v
........\........\...\.......\aes_inv_sbox.v
........\........\...\.......\aes_key_expand_128.v
........\........\...\.......\aes_rcon.v
........\........\...\.......\aes_sbox.v
........\........\...\.......\timescale.v
........\........\...\.......\transcript
........\........\sim\rtl_sim\bin\Makefile
........\........\...\.......\run\waves\waves.do
........\........\.yn\bin\comp.dc
........\........\...\...\design_spec.dc
........\........\...\...\lib_spec.dc
........\........\...\...\read.dc
........\........\vim_session.vim
........\aes_core.tar.gz
........\OPENCORES.files\dotty.gif
........\...............\title_logo.gif
........\OPENCORES.htm
........\aes_core\sim\rtl_sim\run\waves
........\........\...\.......\bin
........\........\...\.......\run
........\........\bench\verilog
........\........\rtl\verilog
........\........\sim\rtl_sim
........\........\.yn\bin
........\........\bench
........\........\doc
........\........\rtl
........\........\sim
........\........\syn
........\aes_core
........\OPENCORES.files
aes core