文件名称:AMBA-Bus_Verilog_Model
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该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.相关搜索： ahb
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下载文件列表
AMBA Bus_Verilog_Model\ahb_apb_bridge\rtl\ahb_apb_bridge.v
......................\.....rbiter\rtl\ahb_arbiter.v
......................\...........\...\ahb_decoder.v
......................\...........\...\ahb_default_master.v
......................\...........\...\ahb_default_slave.v
......................\...........\...\ahb_mast_mux.v
......................\...........\...\ahb_slave_mux.v
......................\....rom_slave\rtl\ahb_rom_slave.v
......................\....sram_slave\rtl\ahb_sram_slave.v
......................\defines\ahb_defines.v
......................\.......\apb_defines.v
......................\ahb_apb_bridge\rtl
......................\.....rbiter\rtl
......................\....rom_slave\rtl
......................\....sram_slave\rtl
......................\ahb_apb_bridge
......................\ahb_arbiter
......................\ahb_rom_slave
......................\ahb_sram_slave
......................\defines
AMBA Bus_Verilog_Model
......................\.....rbiter\rtl\ahb_arbiter.v
......................\...........\...\ahb_decoder.v
......................\...........\...\ahb_default_master.v
......................\...........\...\ahb_default_slave.v
......................\...........\...\ahb_mast_mux.v
......................\...........\...\ahb_slave_mux.v
......................\....rom_slave\rtl\ahb_rom_slave.v
......................\....sram_slave\rtl\ahb_sram_slave.v
......................\defines\ahb_defines.v
......................\.......\apb_defines.v
......................\ahb_apb_bridge\rtl
......................\.....rbiter\rtl
......................\....rom_slave\rtl
......................\....sram_slave\rtl
......................\ahb_apb_bridge
......................\ahb_arbiter
......................\ahb_rom_slave
......................\ahb_sram_slave
......................\defines
AMBA Bus_Verilog_Model