文件名称:Verilog_SPI_SD_controler
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 3.95mb
- 下载次数：
- 0次
- 提 供 者：
- hechu******
- 相关连接：
- 无
- 下载说明：
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介绍说明－－下载内容均来自于网络，请自行研究使用
非常全面详细的SPI接口的verilog源代码-Very comprehensive and detailed source code verilog SPI interface
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Verilog_SPI_SD_controler\sdcard_mass_storage_controller\branches\conf\authz
........................\..............................\........\....\passwd
........................\..............................\........\....\svnserve.conf
........................\..............................\........\db\current
........................\..............................\........\..\format
........................\..............................\........\..\fs-type
........................\..............................\........\..\fsfs.conf
........................\..............................\........\..\min-unpacked-rev
........................\..............................\........\..\rep-cache.db
........................\..............................\........\..\..vprops\0\0
........................\..............................\........\..\...s\0\0
........................\..............................\........\..\txn-current
........................\..............................\........\..\txn-current-lock
........................\..............................\........\..\uuid
........................\..............................\........\..\write-lock
........................\..............................\........\format
........................\..............................\........\hooks\post-commit.tmpl
........................\..............................\........\.....\post-lock.tmpl
........................\..............................\........\.....\post-revprop-change.tmpl
........................\..............................\........\.....\post-unlock.tmpl
........................\..............................\........\.....\pre-commit.tmpl
........................\..............................\........\.....\pre-lock.tmpl
........................\..............................\........\.....\pre-revprop-change.tmpl
........................\..............................\........\.....\pre-unlock.tmpl
........................\..............................\........\.....\start-commit.tmpl
........................\..............................\........\locks\db-logs.lock
........................\..............................\........\.....\db.lock
........................\..............................\........\README.txt
........................\..............................\trunk\backend\Actel\Block\versatile_fifo_dptam_dw\compile_report.log
........................\..............................\.....\.......\.....\.....\.......................\datasheet_report.log
........................\..............................\.....\.......\.....\.....\.......................\global_report.log
........................\..............................\.....\.......\.....\.....\.......................\header_report.log
........................\..............................\.....\.......\.....\.....\.......................\interface_report.log
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cdb
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cxf
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_pre.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_sim.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_syn.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_usedLocations.pdc
........................\..............................\.....\.......\.....\proasic3_redused.v
........................\..............................\.....\.ench\sdc_dma\verilog\sdModel.v
........................\..............................\.....\.....\.......\.......\SD_controller_top_tb.v
........................\.............................
........................\..............................\........\....\passwd
........................\..............................\........\....\svnserve.conf
........................\..............................\........\db\current
........................\..............................\........\..\format
........................\..............................\........\..\fs-type
........................\..............................\........\..\fsfs.conf
........................\..............................\........\..\min-unpacked-rev
........................\..............................\........\..\rep-cache.db
........................\..............................\........\..\..vprops\0\0
........................\..............................\........\..\...s\0\0
........................\..............................\........\..\txn-current
........................\..............................\........\..\txn-current-lock
........................\..............................\........\..\uuid
........................\..............................\........\..\write-lock
........................\..............................\........\format
........................\..............................\........\hooks\post-commit.tmpl
........................\..............................\........\.....\post-lock.tmpl
........................\..............................\........\.....\post-revprop-change.tmpl
........................\..............................\........\.....\post-unlock.tmpl
........................\..............................\........\.....\pre-commit.tmpl
........................\..............................\........\.....\pre-lock.tmpl
........................\..............................\........\.....\pre-revprop-change.tmpl
........................\..............................\........\.....\pre-unlock.tmpl
........................\..............................\........\.....\start-commit.tmpl
........................\..............................\........\locks\db-logs.lock
........................\..............................\........\.....\db.lock
........................\..............................\........\README.txt
........................\..............................\trunk\backend\Actel\Block\versatile_fifo_dptam_dw\compile_report.log
........................\..............................\.....\.......\.....\.....\.......................\datasheet_report.log
........................\..............................\.....\.......\.....\.....\.......................\global_report.log
........................\..............................\.....\.......\.....\.....\.......................\header_report.log
........................\..............................\.....\.......\.....\.....\.......................\interface_report.log
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cdb
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw.cxf
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_pre.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_sim.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_syn.v
........................\..............................\.....\.......\.....\.....\.......................\versatile_fifo_dptam_dw_usedLocations.pdc
........................\..............................\.....\.......\.....\proasic3_redused.v
........................\..............................\.....\.ench\sdc_dma\verilog\sdModel.v
........................\..............................\.....\.....\.......\.......\SD_controller_top_tb.v
........................\.............................