文件名称:clock1
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基于FPGA的数字钟设计代码，可显示时间，报时，调时，在开发板EP3C16Q240C8上可实现。-FPGA-based digital clock design code, time, timekeeping, tune in development board EP3C16Q240C8, to achieve.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock1\chronopher.bsf
......\chronopher.vhd
......\chronopher.vhd.bak
......\clkdivider.bsf
......\clkdivider.vhd
......\clkdivider.vhd.bak
......\clock1.asm.rpt
......\clock1.bdf
......\clock1.cdf
......\clock1.done
......\clock1.fit.rpt
......\clock1.fit.smsg
......\clock1.fit.summary
......\clock1.flow.rpt
......\clock1.map.rpt
......\clock1.map.summary
......\clock1.pin
......\clock1.qpf
......\clock1.qsf
......\clock1.qws
......\clock1.sim.rpt
......\clock1.sof
......\clock1.sta.rpt
......\clock1.sta.summary
......\clock1.vhd
......\clock1.vhd.bak
......\clock1.vwf
......\controller.bsf
......\controller.vhd
......\controller.vhd.bak
......\counter.bsf
......\counter.vhd
......\counter.vhd.bak
......\db\clock1.asm.qmsg
......\..\clock1.asm.rdb
......\..\clock1.asm_labs.ddb
......\..\clock1.cbx.xml
......\..\clock1.cmp.bpm
......\..\clock1.cmp.cbp
......\..\clock1.cmp.cdb
......\..\clock1.cmp.ecobp
......\..\clock1.cmp.hdb
......\..\clock1.cmp.kpt
......\..\clock1.cmp.logdb
......\..\clock1.cmp.rdb
......\..\clock1.cmp_merge.kpt
......\..\clock1.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
......\..\clock1.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
......\..\clock1.db_info
......\..\clock1.eco.cdb
......\..\clock1.eds_overflow
......\..\clock1.fit.qmsg
......\..\clock1.fnsim.hdb
......\..\clock1.fnsim.qmsg
......\..\clock1.hier_info
......\..\clock1.hif
......\..\clock1.lpc.html
......\..\clock1.lpc.rdb
......\..\clock1.lpc.txt
......\..\clock1.map.bpm
......\..\clock1.map.cdb
......\..\clock1.map.ecobp
......\..\clock1.map.hdb
......\..\clock1.map.kpt
......\..\clock1.map.logdb
......\..\clock1.map.qmsg
......\..\clock1.map_bb.cdb
......\..\clock1.map_bb.hdb
......\..\clock1.map_bb.logdb
......\..\clock1.pre_map.cdb
......\..\clock1.pre_map.hdb
......\..\clock1.rtlv.hdb
......\..\clock1.rtlv_sg.cdb
......\..\clock1.rtlv_sg_swap.cdb
......\..\clock1.sgdiff.cdb
......\..\clock1.sgdiff.hdb
......\..\clock1.sim.cvwf
......\..\clock1.sim.hdb
......\..\clock1.sim.qmsg
......\..\clock1.sim.rdb
......\..\clock1.simfam
......\..\clock1.sld_design_entry.sci
......\..\clock1.sld_design_entry_dsc.sci
......\..\clock1.smart_action.txt
......\..\clock1.sta.qmsg
......\..\clock1.sta.rdb
......\..\clock1.sta_cmp.8_slow_1200mv_85c.tdb
......\..\clock1.syn_hier_info
......\..\clock1.tiscmp.fast_1200mv_0c.ddb
......\..\clock1.tiscmp.slow_1200mv_0c.ddb
......\..\clock1.tiscmp.slow_1200mv_85c.ddb
......\..\clock1.tis_db_list.ddb
......\..\clock1.tmw_info
......\..\logic_util_heursitic.dat
......\..\mux_1sc.tdf
......\..\mux_7qc.tdf
......\..\mux_cqc.tdf
......\..\mux_src.tdf
......\..\prev_cmp_clock1.asm.qmsg
......\..\prev_cmp_clock1.fit.qmsg