文件名称:fcout
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频率计源代码,性能很好,verilog写的,顶层原理图,底层语言写的,效果很好,开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus相关搜索: verilog
频率计
频率计
verilog
verilog
频率计
Verilog
Source
code
棰戠巼璁?p=
频率计
自动
频率计
频率计
verilog
verilog
频率计
Verilog
Source
code
棰戠巼璁?p=
频率计
自动
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fcout
.....\cmp_state.ini
.....\counter_24b.bsf
.....\counter_24b.v
.....\db
.....\..\fcout.asm.qmsg
.....\..\fcout.cbx.xml
.....\..\fcout.cmp.cdb
.....\..\fcout.cmp.hdb
.....\..\fcout.cmp.rdb
.....\..\fcout.cmp.tdb
.....\..\fcout.cmp0.ddb
.....\..\fcout.db_info
.....\..\fcout.eco.cdb
.....\..\fcout.eds_overflow
.....\..\fcout.fit.qmsg
.....\..\fcout.hier_info
.....\..\fcout.hif
.....\..\fcout.map.cdb
.....\..\fcout.map.hdb
.....\..\fcout.map.qmsg
.....\..\fcout.pre_map.cdb
.....\..\fcout.pre_map.hdb
.....\..\fcout.psp
.....\..\fcout.rtlv.hdb
.....\..\fcout.rtlv_sg.cdb
.....\..\fcout.rtlv_sg_swap.cdb
.....\..\fcout.sgdiff.cdb
.....\..\fcout.sgdiff.hdb
.....\..\fcout.sim.hdb
.....\..\fcout.sim.qmsg
.....\..\fcout.sim.rdb
.....\..\fcout.sim.vwf
.....\..\fcout.sld_design_entry.sci
.....\..\fcout.sld_design_entry_dsc.sci
.....\..\fcout.syn_hier_info
.....\..\fcout.tan.qmsg
.....\..\fcout_cmp.qrpt
.....\..\fcout_sim.qrpt
.....\display.bdf
.....\display.bsf
.....\display.v
.....\div3.bsf
.....\div3.v
.....\dividers.bdf
.....\dividers.bsf
.....\fcout.asm.rpt
.....\fcout.bdf
.....\fcout.cdf
.....\fcout.done
.....\fcout.fit.eqn
.....\fcout.fit.rpt
.....\fcout.fit.summary
.....\fcout.flow.rpt
.....\fcout.map.eqn
.....\fcout.map.rpt
.....\fcout.map.summary
.....\fcout.pin
.....\fcout.pof
.....\fcout.ppl
.....\fcout.qpf
.....\fcout.qsf
.....\fcout.qws
.....\fcout.sim.rpt
.....\fcout.sof
.....\fcout.tan.rpt
.....\fcout.tan.summary
.....\fcout.vwf
.....\Half_freq.bsf
.....\Half_freq.v
.....\mode.bsf
.....\mode.v
.....\ten_divider.bsf
.....\ten_divider.v
.....\cmp_state.ini
.....\counter_24b.bsf
.....\counter_24b.v
.....\db
.....\..\fcout.asm.qmsg
.....\..\fcout.cbx.xml
.....\..\fcout.cmp.cdb
.....\..\fcout.cmp.hdb
.....\..\fcout.cmp.rdb
.....\..\fcout.cmp.tdb
.....\..\fcout.cmp0.ddb
.....\..\fcout.db_info
.....\..\fcout.eco.cdb
.....\..\fcout.eds_overflow
.....\..\fcout.fit.qmsg
.....\..\fcout.hier_info
.....\..\fcout.hif
.....\..\fcout.map.cdb
.....\..\fcout.map.hdb
.....\..\fcout.map.qmsg
.....\..\fcout.pre_map.cdb
.....\..\fcout.pre_map.hdb
.....\..\fcout.psp
.....\..\fcout.rtlv.hdb
.....\..\fcout.rtlv_sg.cdb
.....\..\fcout.rtlv_sg_swap.cdb
.....\..\fcout.sgdiff.cdb
.....\..\fcout.sgdiff.hdb
.....\..\fcout.sim.hdb
.....\..\fcout.sim.qmsg
.....\..\fcout.sim.rdb
.....\..\fcout.sim.vwf
.....\..\fcout.sld_design_entry.sci
.....\..\fcout.sld_design_entry_dsc.sci
.....\..\fcout.syn_hier_info
.....\..\fcout.tan.qmsg
.....\..\fcout_cmp.qrpt
.....\..\fcout_sim.qrpt
.....\display.bdf
.....\display.bsf
.....\display.v
.....\div3.bsf
.....\div3.v
.....\dividers.bdf
.....\dividers.bsf
.....\fcout.asm.rpt
.....\fcout.bdf
.....\fcout.cdf
.....\fcout.done
.....\fcout.fit.eqn
.....\fcout.fit.rpt
.....\fcout.fit.summary
.....\fcout.flow.rpt
.....\fcout.map.eqn
.....\fcout.map.rpt
.....\fcout.map.summary
.....\fcout.pin
.....\fcout.pof
.....\fcout.ppl
.....\fcout.qpf
.....\fcout.qsf
.....\fcout.qws
.....\fcout.sim.rpt
.....\fcout.sof
.....\fcout.tan.rpt
.....\fcout.tan.summary
.....\fcout.vwf
.....\Half_freq.bsf
.....\Half_freq.v
.....\mode.bsf
.....\mode.v
.....\ten_divider.bsf
.....\ten_divider.v