文件名称:FIFO_BEFORE
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是基于fpga的FIFO乒乓操作,后面是与SDRAM接口的,这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram相关搜索: 乒乓
fifo
fpga
pll
FPGA
接口
sdram
fpga
SDRAM
fpga
fifo
FPGA
ram
FPGA
fpga
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fifo
fpga
pll
FPGA
接口
sdram
fpga
SDRAM
fpga
fifo
FPGA
ram
FPGA
fpga
sdram
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下载文件列表
FIFO_BEFORE
...........\.lso
...........\fifo.ant
...........\fifo.fdo
...........\fifo.jhd
...........\fifo.tbw
...........\fifo.udo
...........\fifo.vhw
...........\fifo.xwv
...........\fifo.xwv_bak
...........\fifo_before.ant
...........\fifo_before.cmd_log
...........\fifo_before.ise
...........\fifo_before.ise_ISE_Backup
...........\fifo_before.jhd
...........\fifo_before.lso
...........\fifo_before.ngc
...........\fifo_before.ngr
...........\fifo_before.ntrc_log
...........\fifo_before.prj
...........\fifo_before.stx
...........\fifo_before.syr
...........\fifo_before.tbw
...........\fifo_before.vhd
...........\fifo_before.xst
...........\fifo_before.xwv
...........\fifo_before.xwv_bak
...........\fifo_before_bencher.prj
...........\fifo_before_summary.html
...........\fifo_bencher.prj
...........\pepExtractor.prj
...........\results.txt
...........\transcript
...........\vsim.wlf
...........\work
...........\....\fifo
...........\....\....\testbench_arch.asm
...........\....\....\testbench_arch.dat
...........\....\....\_primary.dat
...........\....\fifo_before
...........\....\...........\behavioral.asm
...........\....\...........\behavioral.dat
...........\....\...........\_primary.dat
...........\....\_info
...........\xst
...........\...\dump.xst
...........\...\........\fifo_before.prj
...........\...\........\...............\ngx
...........\...\........\...............\...\notopt
...........\...\........\...............\...\opt
...........\...\........\...............\ntrc.scr
...........\...\projnav.tmp
...........\...\work
...........\...\....\hdllib.ref
...........\...\....\hdpdeps.ref
...........\...\....\sub00
...........\...\....\.....\vhpl00.vho
...........\...\....\.....\vhpl01.vho
...........\_xmsgs
...........\......\xst.xmsgs
...........\.lso
...........\fifo.ant
...........\fifo.fdo
...........\fifo.jhd
...........\fifo.tbw
...........\fifo.udo
...........\fifo.vhw
...........\fifo.xwv
...........\fifo.xwv_bak
...........\fifo_before.ant
...........\fifo_before.cmd_log
...........\fifo_before.ise
...........\fifo_before.ise_ISE_Backup
...........\fifo_before.jhd
...........\fifo_before.lso
...........\fifo_before.ngc
...........\fifo_before.ngr
...........\fifo_before.ntrc_log
...........\fifo_before.prj
...........\fifo_before.stx
...........\fifo_before.syr
...........\fifo_before.tbw
...........\fifo_before.vhd
...........\fifo_before.xst
...........\fifo_before.xwv
...........\fifo_before.xwv_bak
...........\fifo_before_bencher.prj
...........\fifo_before_summary.html
...........\fifo_bencher.prj
...........\pepExtractor.prj
...........\results.txt
...........\transcript
...........\vsim.wlf
...........\work
...........\....\fifo
...........\....\....\testbench_arch.asm
...........\....\....\testbench_arch.dat
...........\....\....\_primary.dat
...........\....\fifo_before
...........\....\...........\behavioral.asm
...........\....\...........\behavioral.dat
...........\....\...........\_primary.dat
...........\....\_info
...........\xst
...........\...\dump.xst
...........\...\........\fifo_before.prj
...........\...\........\...............\ngx
...........\...\........\...............\...\notopt
...........\...\........\...............\...\opt
...........\...\........\...............\ntrc.scr
...........\...\projnav.tmp
...........\...\work
...........\...\....\hdllib.ref
...........\...\....\hdpdeps.ref
...........\...\....\sub00
...........\...\....\.....\vhpl00.vho
...........\...\....\.....\vhpl01.vho
...........\_xmsgs
...........\......\xst.xmsgs