压缩包 : 113172214design_and_test_veriloghdl.rar 列表
Example-2-1\HelloVlog.v
Example-3-1\FullAdd.v
Example-3-1\transcript
Example-3-2\FullAdd.v
Example-3-3\CRC10.v
Example-4-1\cnt.prd
Example-4-1\cnt.prj
Example-4-1\rev_1\cnt1.edf
Example-4-1\rev_1\cnt1.fse
Example-4-1\rev_1\cnt1.srm
Example-4-1\rev_1\cnt1.srr
Example-4-1\rev_1\cnt1.srs
Example-4-1\rev_1\cnt1.tlg
Example-4-1\rev_1\cnt2.edf
Example-4-1\rev_1\cnt2.fse
Example-4-1\rev_1\cnt2.srm
Example-4-1\rev_1\cnt2.srr
Example-4-1\rev_1\cnt2.srs
Example-4-1\rev_1\cnt2.tlg
Example-4-1\rev_1\cnt3.edf
Example-4-1\rev_1\cnt3.fse
Example-4-1\rev_1\cnt3.srm
Example-4-1\rev_1\cnt3.srr
Example-4-1\rev_1\cnt3.srs
Example-4-1\rev_1\cnt3.tlg
Example-4-1\rev_1\syntmp\cnt1.plg
Example-4-1\rev_1\syntmp\cnt2.msg
Example-4-1\rev_1\syntmp\cnt2.plg
Example-4-1\rev_1\syntmp\cnt3.msg
Example-4-1\rev_1\syntmp\cnt3.plg
Example-4-1\source\cnt1.v
Example-4-1\source\cnt2.v
Example-4-1\source\cnt3.v
Example-4-1\source\syntmp.msg
Example-4-1\示例说明.doc
Example-4-4\reg_counter.prd
Example-4-4\reg_counter.prj
Example-4-4\reg_counter.v
Example-4-4\rev_2\reg_counter.edf
Example-4-4\rev_2\reg_counter.fse
Example-4-4\rev_2\reg_counter.ncf
Example-4-4\rev_2\reg_counter.srd
Example-4-4\rev_2\reg_counter.srm
Example-4-4\rev_2\reg_counter.srr
Example-4-4\rev_2\reg_counter.srs
Example-4-4\rev_2\reg_counter.tlg
Example-4-4\rev_2\rpt_reg_counter.areasrr
Example-4-4\rev_2\rpt_reg_counter_areasrr.htm
Example-4-4\rev_2\syntmp\reg_counter.msg
Example-4-4\rev_2\syntmp\reg_counter.plg
Example-4-4\rev_2\verif\reg_counter.vif
Example-4-4\sim\reg_counter.v
Example-4-4\source\reg_counter.v
Example-4-4\示例说明.doc
Example-4-7\clock_edge.prd
Example-4-7\clock_edge.prj
Example-4-7\clock_edge.v
Example-4-7\rev_2\clock_edge.edn
Example-4-7\rev_2\clock_edge.fse
Example-4-7\rev_2\clock_edge.prf
Example-4-7\rev_2\clock_edge.srm
Example-4-7\rev_2\clock_edge.srr
Example-4-7\rev_2\clock_edge.srs
Example-4-7\rev_2\clock_edge.tlg
Example-4-7\rev_2\generic.fse
Example-4-7\rev_2\generic.srd
Example-4-7\rev_2\syntmp\clock_edge.msg
Example-4-7\rev_2\syntmp\clock_edge.plg
Example-4-7\sim\clock_edge.v
Example-4-7\sim\clock_edge_tb.v
Example-4-7\sim\sim_clock_edge.cr.mti
Example-4-7\sim\sim_clock_edge.mpf
Example-4-7\sim\transcript
Example-4-7\sim\vsim.wlf
Example-4-7\sim\wave.do
Example-4-7\sim\work\_info
Example-4-7\sim\work\clock_edge\_primary.dat
Example-4-7\sim\work\clock_edge\_primary.vhd
Example-4-7\sim\work\clock_edge\verilog.asm
Example-4-7\sim\work\clock_edge_tb\_primary.dat
Example-4-7\sim\work\clock_edge_tb\_primary.vhd
Example-4-7\sim\work\clock_edge_tb\verilog.asm
Example-4-7\source\clock_edge.v
Example-4-7\source\clock_edge_tb.v
Example-4-7\syntmp.msg
Example-4-7\示例说明.doc
Example-4-8\decode_cmb.prd
Example-4-8\decode_cmb.prj
Example-4-8\decode_cmb.v
Example-4-8\decode_cmb2.v
Example-4-8\rev_2\decode_cmb.edn
Example-4-8\rev_2\decode_cmb.fse
Example-4-8\rev_2\decode_cmb.prf
Example-4-8\rev_2\decode_cmb.srm
Example-4-8\rev_2\decode_cmb.srr
Example-4-8\rev_2\decode_cmb.srs
Example-4-8\rev_2\decode_cmb.tlg
Example-4-8\rev_2\decode_cmb2.edn
Example-4-8\rev_2\decode_cmb2.fse
Example-4-8\rev_2\decode_cmb2.prf
Example-4-8\rev_2\decode_cmb2.srm
Example-4-8\rev_2\decode_cmb2.srr
Example-4-8\rev_2\decode_cmb2.srs
Example-4-8\rev_2\decode_cmb2.tlg
Example-4-8\rev_2\generic.fse
Example-4-8\rev_2\generic.srd
Example-4-8\rev_2\syntmp\decode_cmb.plg
Example-4-8\rev_2\syntmp\decode_cmb2.msg
Example-4-8\rev_2\syntmp\decode_cmb2.plg
Example-4-8\sim\decode_cmb.cr.mti
Example-4-8\sim\decode_cmb.mpf
Example-4-8\sim\decode_cmb.v
Example-4-8\sim\decode_cmb2.v
Example-4-8\sim\decode_cmb_tb.v
Example-4-8\sim\transcript
Example-4-8\sim\vsim.wlf
Example-4-8\sim\work\_info
Example-4-8\sim\work\decode_cmb\_primary.dat
Example-4-8\sim\work\decode_cmb\_primary.vhd
Example-4-8\sim\work\decode_cmb\verilog.asm
Example-4-8\sim\work\decode_cmb2\_primary.dat
Example-4-8\sim\work\decode_cmb2\_primary.vhd
Example-4-8\sim\work\decode_cmb2\verilog.asm
Example-4-8\sim\work\decode_cmb_tb\_primary.dat
Example-4-8\sim\work\decode_cmb_tb\_primary.vhd
Example-4-8\sim\work\decode_cmb_tb\verilog.asm
Example-4-8\source\decode_cmb.v
Example-4-8\source\decode_cmb2.v
Example-4-8\source\decode_cmb_tb.v
Example-4-8\示例说明.doc
Example-4-10\bibus\bibus.prd
Example-4-10\bibus\bibus.prj
Example-4-10\bibus\bibus.v
Example-4-10\bibus\decode.v
Example-4-10\bibus\rev_1\bibus.fse
Example-4-10\bibus\rev_1\bibus.srd
Example-4-10\bibus\rev_1\bibus.srm
Example-4-10\bibus\rev_1\bibus.srr
Example-4-10\bibus\rev_1\bibus.srs
Example-4-10\bibus\rev_1\bibus.sxr
Example-4-10\bibus\rev_1\bibus.tcl
Example-4-10\bibus\rev_1\bibus.tlg
Example-4-10\bibus\rev_1\bibus.vqm
Example-4-10\bibus\rev_1\bibus.xrf
Example-4-10\bibus\rev_1\bibus_cons.tcl
Example-4-10\bibus\rev_1\bibus_rm.tcl
Example-4-10\bibus\rev_1\rpt_bibus.areasrr
Example-4-10\bibus\rev_1\rpt_bibus_areasrr.htm
Example-4-10\bibus\rev_1\syntmp\bibus.msg
Example-4-10\bibus\rev_1\syntmp\bibus.plg
Example-4-10\bibus\rev_1\syntmp\bibus_cons_ui.tcl
Example-4-10\bibus\rev_1\verif\bibus.vif
Example-4-10\bibus\syntmp.msg
Example-4-10\complex_bibus\complex_bibus.prd
Example-4-10\complex_bibus\complex_bibus.prj
Example-4-10\complex_bibus\complex_bibus.v
Example-4-10\complex_bibus\complex_bibus2.v
Example-4-10\complex_bibus\counter.v
Example-4-10\complex_bibus\decode.v
Example-4-10\complex_bibus\rev_1\AutoConstraint_complex_bibus.sdc
Example-4-10\complex_bibus\rev_1\complex_bibus.fse
Example-4-10\complex_bibus\rev_1\complex_bibus.srd
Example-4-10\complex_bibus\rev_1\complex_bibus.srm
Example-4-10\complex_bibus\rev_1\complex_bibus.srr
Example-4-10\complex_bibus\rev_1\complex_bibus.srs
Example-4-10\complex_bibus\rev_1\complex_bibus.sxr
Example-4-10\complex_bibus\rev_1\complex_bibus.tcl
Example-4-10\complex_bibus\rev_1\complex_bibus.tlg
Example-4-10\complex_bibus\rev_1\complex_bibus.vqm
Example-4-10\complex_bibus\rev_1\complex_bibus.xrf
Example-4-10\complex_bibus\rev_1\complex_bibus2.fse
Example-4-10\complex_bibus\rev_1\complex_bibus2.srd
Example-4-10\complex_bibus\rev_1\complex_bibus2.srm
Example-4-10\complex_bibus\rev_1\complex_bibus2.srr
Example-4-10\complex_bibus\rev_1\complex_bibus2.srs
Example-4-10\complex_bibus\rev_1\complex_bibus2.sxr
Example-4-10\complex_bibus\rev_1\complex_bibus2.tcl
Example-4-10\complex_bibus\rev_1\complex_bibus2.tlg
Example-4-10\complex_bibus\rev_1\complex_bibus2.vqm
Example-4-10\complex_bibus\rev_1\complex_bibus2.xrf
Example-4-10\complex_bibus\rev_1\complex_bibus2_cons.tcl
Example-4-10\complex_bibus\rev_1\complex_bibus2_rm.tcl
Example-4-10\complex_bibus\rev_1\complex_bibus_cons.tcl
Example-4-10\complex_bibus\rev_1\complex_bibus_rm.tcl
Example-4-10\complex_bibus\rev_1\decode.srr
Example-4-10\complex_bibus\rev_1\rpt_complex_bibus.areasrr
Example-4-10\complex_bibus\rev_1\rpt_complex_bibus_areasrr.htm
Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus.msg
Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus.plg
Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus2.plg
Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus2_cons_ui.tcl
Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus_cons_ui.tcl
Example-4-10\complex_bibus\rev_1\verif\complex_bibus.vif
Example-4-10\complex_bibus\rev_1\verif\complex_bibus2.vif
Example-4-10\complex_bibus\syntmp.msg
Example-4-10\source\bibus.v
Example-4-10\source\complex_bibus.v
Example-4-10\source\complex_bibus2.v
Example-4-10\source\counter.v
Example-4-10\source\decode.v
Example-4-10\示例说明.doc
Example-4-11\mux.prd
Example-4-11\mux.prj
Example-4-11\mux.v
Example-4-11\mux2.v
Example-4-11\rev_1\AutoConstraint_mux.sdc
Example-4-11\rev_1\generic.fse
Example-4-11\rev_1\generic.srd
Example-4-11\rev_1\mux.edf
Example-4-11\rev_1\mux.edn
Example-4-11\rev_1\mux.fse
Example-4-11\rev_1\mux.ncf
Example-4-11\rev_1\mux.prf
Example-4-11\rev_1\mux.srd
Example-4-11\rev_1\mux.srm
Example-4-11\rev_1\mux.srr
Example-4-11\rev_1\mux.srs
Example-4-11\rev_1\mux.sxr
Example-4-11\rev_1\mux.tcl
Example-4-11\rev_1\mux.tlg
Example-4-11\rev_1\mux.vqm
Example-4-11\rev_1\mux.xrf
Example-4-11\rev_1\mux2.edf
Example-4-11\rev_1\mux2.fse
Example-4-11\rev_1\mux2.ncf
Example-4-11\rev_1\mux2.srd
Example-4-11\rev_1\mux2.srm
Example-4-11\rev_1\mux2.srr
Example-4-11\rev_1\mux2.srs
Example-4-11\rev_1\mux2.tlg
Example-4-11\rev_1\mux_cons.tcl
Example-4-11\rev_1\mux_rm.tcl
Example-4-11\rev_1\rpt_mux.areasrr
Example-4-11\rev_1\rpt_mux_areasrr.htm
Example-4-11\rev_1\syntmp\mux.plg
Example-4-11\rev_1\syntmp\mux2.msg
Example-4-11\rev_1\syntmp\mux2.plg
Example-4-11\rev_1\syntmp\mux_cons_ui.tcl
Example-4-11\rev_1\verif\mux.vif
Example-4-11\rev_1\verif\mux2.vif
Example-4-11\source\mux.v
Example-4-11\source\mux2.v
Example-4-11\syntmp.msg
Example-4-11\示例说明.doc
Example-4-13\ram_basic\ram_basic.prd
Example-4-13\ram_basic\ram_basic.prj
Example-4-13\ram_basic\ram_basic.v
Example-4-13\ram_basic\rev_2\.recordref
Example-4-13\ram_basic\rev_2\AutoConstraint_ram_basic.sdc
Example-4-13\ram_basic\rev_2\ram_basic.edf
Example-4-13\ram_basic\rev_2\ram_basic.fse
Example-4-13\ram_basic\rev_2\ram_basic.ncf
Example-4-13\ram_basic\rev_2\ram_basic.srd
Example-4-13\ram_basic\rev_2\ram_basic.srm
Example-4-13\ram_basic\rev_2\ram_basic.srr
Example-4-13\ram_basic\rev_2\ram_basic.srs
Example-4-13\ram_basic\rev_2\ram_basic.tlg
Example-4-13\ram_basic\rev_2\rpt_ram_basic.areasrr
Example-4-13\ram_basic\rev_2\rpt_ram_basic_areasrr.htm
Example-4-13\ram_basic\rev_2\syntmp\ram_basic.msg
Example-4-13\ram_basic\rev_2\syntmp\ram_basic.plg
Example-4-13\ram_basic\rev_2\traplog.tlg
Example-4-13\ram_basic\rev_2\verif\ram_basic.vif
Example-4-13\sim\ram_basic.cr.mti
Example-4-13\sim\ram_basic.mpf
Example-4-13\sim\ram_basic.v
Example-4-13\sim\ram_basic_tb.v
Example-4-13\sim\transcript
Example-4-13\sim\vsim.wlf
Example-4-13\sim\wave.do
Example-4-13\sim\work\_info
Example-4-13\sim\work\ram_basic\_primary.dat
Example-4-13\sim\work\ram_basic\_primary.vhd
Example-4-13\sim\work\ram_basic\verilog.asm
Example-4-13\sim\work\ram_basic_tb\_primary.dat
Example-4-13\sim\work\ram_basic_tb\_primary.vhd
Example-4-13\sim\work\ram_basic_tb\verilog.asm
Example-4-13\source\ram_basic.v
Example-4-13\示例说明.doc
Example-4-14\clk_3div\clk_3div.v
Example-4-14\clk_3div\clk_3div_tb.v
Example-4-14\clk_3div\sim\clk_div3.cr.mti
Example-4-14\clk_3div\sim\clk_div3.mpf
Example-4-14\clk_3div\sim\vsim.wlf
Example-4-14\clk_3div\sim\wave.do
Example-4-14\clk_3div\sim\work\_info
Example-4-14\clk_3div\sim\work\clk_3div\_primary.dat
Example-4-14\clk_3div\sim\work\clk_3div\_primary.vhd
Example-4-14\clk_3div\sim\work\clk_3div\verilog.asm
Example-4-14\clk_3div\sim\work\clk_3div_tb\_primary.dat
Example-4-14\clk_3div\sim\work\clk_3div_tb\_primary.vhd
Example-4-14\clk_3div\sim\work\clk_3div_tb\verilog.asm
Example-4-14\clk_3div\synthesis\clk_div3.prd
Example-4-14\clk_3div\synthesis\clk_div3.prj
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.edf
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.fse
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srm
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srr
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srs
Example-4-14\clk_3div\synthesis\rev_1\clk_3div.tlg
Example-4-14\clk_3div\synthesis\rev_1\syntmp\clk_3div.msg
Example-4-14\clk_3div\synthesis\rev_1\syntmp\clk_3div.plg
Example-4-14\clk_div_phase\clk_div_phase.prd
Example-4-14\clk_div_phase\clk_div_phase.prj
Example-4-14\clk_div_phase\clk_div_phase.v
Example-4-14\clk_div_phase\clk_div_phase_tb.v
Example-4-14\clk_div_phase\rev_1\AutoConstraint_clk_div_phase.sdc
Example-4-14\clk_div_phase\rev_1\clk_div_phase.edf
Example-4-14\clk_div_phase\rev_1\clk_div_phase.fse
Example-4-14\clk_div_phase\rev_1\clk_div_phase.ncf
Example-4-14\clk_div_phase\rev_1\clk_div_phase.srd
Example-4-14\clk_div_phase\rev_1\clk_div_phase.srm
Example-4-14\clk_div_phase\rev_1\clk_div_phase.srr
Example-4-14\clk_div_phase\rev_1\clk_div_phase.srs
Example-4-14\clk_div_phase\rev_1\clk_div_phase.tlg
Example-4-14\clk_div_phase\rev_1\rpt_clk_div_phase.areasrr
Example-4-14\clk_div_phase\rev_1\rpt_clk_div_phase_areasrr.htm
Example-4-14\clk_div_phase\rev_1\syntmp\clk_div_phase.msg
Example-4-14\clk_div_phase\rev_1\syntmp\clk_div_phase.plg
Example-4-14\clk_div_phase\rev_1\verif\clk_div_phase.vif
Example-4-14\clk_div_phase\sim\clk_div.cr.mti
Example-4-14\clk_div_phase\sim\clk_div.mpf
Example-4-14\clk_div_phase\sim\transcript
Example-4-14\clk_div_phase\sim\vsim.wlf
Example-4-14\clk_div_phase\sim\wave.do
Example-4-14\clk_div_phase\sim\work\_info
Example-4-14\clk_div_phase\sim\work\clk_div_phase\_primary.dat
Example-4-14\clk_div_phase\sim\work\clk_div_phase\_primary.vhd
Example-4-14\clk_div_phase\sim\work\clk_div_phase\verilog.asm
Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb\_primary.dat
Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb\_primary.vhd
Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb\verilog.asm
Example-4-14\示例说明.doc
Example-4-16\rev_1\AutoConstraint_srl2pal.sdc
Example-4-16\rev_1\rpt_srl2pal.areasrr
Example-4-16\rev_1\rpt_srl2pal_areasrr.htm
Example-4-16\rev_1\srl2pal.edf
Example-4-16\rev_1\srl2pal.fse
Example-4-16\rev_1\srl2pal.ncf
Example-4-16\rev_1\srl2pal.srd
Example-4-16\rev_1\srl2pal.srm
Example-4-16\rev_1\srl2pal.srr
Example-4-16\rev_1\srl2pal.srs
Example-4-16\rev_1\srl2pal.tlg
Example-4-16\rev_1\syntmp\srl2pal.msg
Example-4-16\rev_1\syntmp\srl2pal.plg
Example-4-16\rev_1\verif\srl2pal.vif
Example-4-16\source\srl2pal.v
Example-4-16\srl2pal.prd
Example-4-16\srl2pal.prj
Example-4-16\srl2pal.v
Example-4-16\示例说明.doc
Example-4-17\asyn_rst\asyn_rst.prd
Example-4-17\asyn_rst\asyn_rst.prj
Example-4-17\asyn_rst\asyn_rst.v
Example-4-17\asyn_rst\rev_1\AutoConstraint_asyn_rst.sdc
Example-4-17\asyn_rst\rev_1\asyn_rst.edn
Example-4-17\asyn_rst\rev_1\asyn_rst.fse
Example-4-17\asyn_rst\rev_1\asyn_rst.prf
Example-4-17\asyn_rst\rev_1\asyn_rst.srm
Example-4-17\asyn_rst\rev_1\asyn_rst.srr
Example-4-17\asyn_rst\rev_1\asyn_rst.srs
Example-4-17\asyn_rst\rev_1\asyn_rst.tlg
Example-4-17\asyn_rst\rev_1\generic.fse
Example-4-17\asyn_rst\rev_1\generic.srd
Example-4-17\asyn_rst\rev_1\syntmp\asyn_rst.msg
Example-4-17\asyn_rst\rev_1\syntmp\asyn_rst.plg
Example-4-17\asyn_rst_syn_release\asyn_rst_syn_release.v
Example-4-17\syn_rst\rev_2\AutoConstraint_syn_rst.sdc
Example-4-17\syn_rst\rev_2\generic.fse
Example-4-17\syn_rst\rev_2\generic.srd
Example-4-17\syn_rst\rev_2\syn_rst.edn
Example-4-17\syn_rst\rev_2\syn_rst.fse
Example-4-17\syn_rst\rev_2\syn_rst.prf
Example-4-17\syn_rst\rev_2\syn_rst.srm
Example-4-17\syn_rst\rev_2\syn_rst.srr
Example-4-17\syn_rst\rev_2\syn_rst.srs
Example-4-17\syn_rst\rev_2\syn_rst.tlg
Example-4-17\syn_rst\rev_2\syntmp\syn_rst.msg
Example-4-17\syn_rst\rev_2\syntmp\syn_rst.plg
Example-4-17\syn_rst\syn_rst.prd
Example-4-17\syn_rst\syn_rst.prj
Example-4-17\syn_rst\syn_rst.v
Example-4-17\syn_rst\syntmp.msg
Example-4-17\示例说明.doc
Example-4-20\case\PrecisionRTL\Thumbs.db
Example-4-20\case\PrecisionRTL\case.psp
Example-4-20\case\PrecisionRTL\case_RTL_schematic.bmp
Example-4-20\case\PrecisionRTL\case_impl_1\case1.edf
Example-4-20\case\PrecisionRTL\case_impl_1\case1.prf
Example-4-20\case\PrecisionRTL\case_impl_1\case1.xdb
Example-4-20\case\PrecisionRTL\case_impl_1\case1_area.rep
Example-4-20\case\PrecisionRTL\case_impl_1\case1_con_rep.sdc
Example-4-20\case\PrecisionRTL\case_impl_1\case1_rtl.ixdb
Example-4-20\case\PrecisionRTL\case_impl_1\case1_tech_con_rep.sdc
Example-4-20\case\PrecisionRTL\case_impl_1\case1_timing.rep
Example-4-20\case\PrecisionRTL\case_impl_1\case_impl_1.psi
Example-4-20\case\PrecisionRTL\case_impl_1\hdlAnalyze_verilogfile
Example-4-20\case\PrecisionRTL\case_impl_1\precision.log
Example-4-20\case\PrecisionRTL\case_impl_1\precision_rtl.sdc
Example-4-20\case\PrecisionRTL\case_impl_1\precision_tech.sdc
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\.rtlc_compile
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Example-4-20\case\PrecisionRTL\case_impl_1\unfolded_operators.txt
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Example-4-20\case\SynplifyPro\Thumbs.db
Example-4-20\case\SynplifyPro\case1.prd
Example-4-20\case\SynplifyPro\case1.prj
Example-4-20\case\SynplifyPro\case_rtl_view.bmp
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Example-4-20\case\SynplifyPro\rev_2\AutoConstraint_case1.sdc
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Example-4-20\case\SynplifyPro\rev_2\syntmp\case1.plg
Example-4-20\case\case1.v
Example-4-20\case\syntmp.msg
Example-4-20\decode\case\case_decode.v
Example-4-20\decode\case\decode_case.psp
Example-4-20\decode\case\decode_case_impl_1\case_decode.edf
Example-4-20\decode\case\decode_case_impl_1\case_decode.prf
Example-4-20\decode\case\decode_case_impl_1\case_decode.xdb
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Example-4-20\decode\case\decode_case_impl_1\decode_case_impl_1.psi
Example-4-20\decode\case\decode_case_impl_1\hdlAnalyze_verilogfile
Example-4-20\decode\case\decode_case_impl_1\precision.log
Example-4-20\decode\case\decode_case_impl_1\precision_rtl.sdc
Example-4-20\decode\case\decode_case_impl_1\precision_tech.sdc
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\.rtlc_compile
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\.top
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\emptymod.list
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Example-4-20\decode\case\precision_schematic.bmp
Example-4-20\decode\case\rev_1\AutoConstraint_case_decode.sdc
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Example-4-20\decode\if_mult\if_mult_schematic.bmp
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Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode.xdb
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Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\.rtlc_compile
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Example-4-20\decode\if_single\precision.log
Example-4-20\decode\if_single\precision.psp
Example-4-20\decode\if_single\precision_impl_1\hdlAnalyze_verilogfile
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Example-4-20\decode\if_single\precision_impl_1\if_single_decode.xdb
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Example-4-20\if_single\PrecisionRTL\if_single_schematic.bmp
Example-4-20\if_single\SynplifyPro\if_single.prd
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Example-4-20\if_single\SynplifyPro\if_single_tech_view.bmp
Example-4-20\if_single\SynplifyPro\rev_2\AutoConstraint_single_if.sdc
Example-4-20\if_single\SynplifyPro\rev_2\generic.fse
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Example-4-21\asyn_bad\asyn_bad.prd
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Example-5-1\FHTPART_resource.bmp
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Example-5-1\示例说明.doc
Example-5-5\latch.prd
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Example-5-5\示例说明.doc
Example-5-6\resource_share.prd
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Example-5-7\mod_copy.prd
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Example-5-7\示例说明.doc
Example-5-8\rev_2\AutoConstraint_shannon_fast.sdc
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Example-5-8\source\shannon_fast.v
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Example-5-8\示例说明.doc
Example-6-1\FSM\state1\rev_1\AutoConstraint_state1.sdc
Example-6-1\FSM\state1\rev_1\NS.txt
Example-6-1\FSM\state1\rev_1\fsmviewer.fsm
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Example-6-1\FSM\state2\rev_1\syntmp\fsm_tmp_cons_ui.tcl
Example-6-1\FSM\state2\rev_1\syntmp\state2.msg
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Example-6-1\FSM\state2\rev_1\syntmp\state2_cons_ui.tcl
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Example-6-1\FSM\state3\rev_2\AutoConstraint_state2.sdc
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Example-6-1\FSM\state3\rev_2\fsmviewer.fsm
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Example-6-1\示例说明.doc
Example-7-1\Proj\MPI.v
Example-7-1\Proj\NorTestBench.v
Example-7-1\Proj\SPRAM.v
Example-7-1\Proj\STM.v
Example-7-1\Proj\Testbench_readme.txt
Example-7-1\Proj\altera_mf.v
Example-7-1\Proj\sim.do
Example-7-1\Proj\wave.do
Example-7-1\示例说明.doc
Example-7-2\Proj\MPI.v
Example-7-2\Proj\NorTestBench.v
Example-7-2\Proj\Read_In_File.txt
Example-7-2\Proj\SPRAM.v
Example-7-2\Proj\STM.v
Example-7-2\Proj\Testbench_readme.txt
Example-7-2\Proj\altera_mf.v
Example-7-2\Proj\sim.do
Example-7-2\Proj\wave.do
Example-7-2\示例说明.doc
Example-7-3\Proj\MPI.v
Example-7-3\Proj\NorTestBench.v
Example-7-3\Proj\Read_In_File.txt
Example-7-3\Proj\SPRAM.v
Example-7-3\Proj\STM.v
Example-7-3\Proj\altera_mf.v
Example-7-3\Proj\harness.v
Example-7-3\Proj\sim.do
Example-7-3\Proj\testcase.v
Example-7-3\Proj\uP_BFM.v
Example-7-3\Proj\wave.do
Example-7-3\示例说明.doc
Example-7-4\Proj\MPI.v
Example-7-4\Proj\NorTestBench.v
Example-7-4\Proj\Read_In_File.txt
Example-7-4\Proj\SPRAM.v
Example-7-4\Proj\STM.v
Example-7-4\Proj\Sim.do
Example-7-4\Proj\altera_mf.v
Example-7-4\Proj\harness.v
Example-7-4\Proj\testcase.v
Example-7-4\Proj\uP_BFM.v
Example-7-4\Proj\wave.do
Example-7-4\示例说明.doc
Example-8-1\sim\INV_DFF.v
Example-8-1\sim\sim.do
Example-8-1\示例说明.doc
Example-8-2\Blocking_LHS_Delay\sim.do
Example-8-2\Blocking_LHS_Delay\tb.v
Example-8-2\Blocking_LHS_Delay\wave.do
Example-8-2\Blocking_RHS_Delay\sim.do
Example-8-2\Blocking_RHS_Delay\tb.v
Example-8-2\Blocking_RHS_Delay\wave.do
Example-8-2\NonBlocking_LHS_Delay\sim.do
Example-8-2\NonBlocking_LHS_Delay\tb.v
Example-8-2\NonBlocking_LHS_Delay\wave.do
Example-8-2\NonBlocking_RHS_Delay\sim.do
Example-8-2\NonBlocking_RHS_Delay\tb.v
Example-8-2\NonBlocking_RHS_Delay\wave.do
Example-8-2\示例说明.doc
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\AREA
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\AREA
Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR\AREA
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR\AREA
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR\AREA
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR\AREA
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\MEM
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\NET
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\NM
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Example-4-20\case\PrecisionRTL\case_impl_1\rtlc_libs\work
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\MEM
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\NET
Example-4-20\decode\case\decode_case_impl_1\rtlc.out\NM
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Example-4-20\decode\case\decode_case_impl_1\rtlc_libs\work
Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR
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Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\NET
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Example-4-20\decode\if_mult\precision_impl_1\rtlc_libs\work
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\MEM
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\NET
Example-4-20\decode\if_single\precision_impl_1\rtlc.out\NM
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Example-4-20\decode\if_single\precision_impl_1\rtlc_libs\work
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\MEM
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\NET
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\NM
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\depend
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc_libs\work
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\EXEM_MACRO_DIR
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\MEM
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\NET
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\NM
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\depend
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc_libs\work
Example-4-14\clk_3div\sim\work\clk_3div
Example-4-14\clk_3div\sim\work\clk_3div_tb
Example-4-14\clk_3div\synthesis\rev_1\syntmp
Example-4-14\clk_div_phase\sim\work\clk_div_phase
Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out
Example-4-20\case\PrecisionRTL\case_impl_1\rtlc_libs
Example-4-20\case\SynplifyPro\rev_2\par_1
Example-4-20\case\SynplifyPro\rev_2\syntmp
Example-4-20\decode\case\decode_case_impl_1\rtlc.out
Example-4-20\decode\case\decode_case_impl_1\rtlc_libs
Example-4-20\decode\case\rev_1\syntmp
Example-4-20\decode\if_mult\precision_impl_1\rtlc.out
Example-4-20\decode\if_mult\precision_impl_1\rtlc_libs
Example-4-20\decode\if_mult\rev_2\syntmp
Example-4-20\decode\if_single\precision_impl_1\rtlc.out
Example-4-20\decode\if_single\precision_impl_1\rtlc_libs
Example-4-20\decode\if_single\rev_1\syntmp
Example-4-20\if_mult\Latch_if_mult\rev_2\syntmp
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc_libs
Example-4-20\if_mult\SynplifyPro\rev_1\syntmp
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out
Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc_libs
Example-4-20\if_single\SynplifyPro\rev_2\syntmp
Example-6-1\FSM\state1\rev_1\syntmp
Example-6-1\FSM\state1\rev_1\verif
Example-6-1\FSM\state2\rev_1\syntmp
Example-6-1\FSM\state2\rev_1\verif
Example-6-1\FSM\state3\rev_2\syntmp
Example-6-1\FSM\state_default\rev_2\syntmp
Example-4-7\sim\work\clock_edge
Example-4-7\sim\work\clock_edge_tb
Example-4-8\sim\work\decode_cmb
Example-4-8\sim\work\decode_cmb2
Example-4-8\sim\work\decode_cmb_tb
Example-4-10\bibus\rev_1\syntmp
Example-4-10\bibus\rev_1\verif
Example-4-10\complex_bibus\rev_1\par_1
Example-4-10\complex_bibus\rev_1\syntmp
Example-4-10\complex_bibus\rev_1\verif
Example-4-13\ram_basic\rev_2\par_1
Example-4-13\ram_basic\rev_2\syntmp
Example-4-13\ram_basic\rev_2\verif
Example-4-13\sim\work\ram_basic
Example-4-13\sim\work\ram_basic_tb
Example-4-14\clk_3div\sim\work
Example-4-14\clk_3div\synthesis\rev_1
Example-4-14\clk_div_phase\rev_1\par_1
Example-4-14\clk_div_phase\rev_1\syntmp
Example-4-14\clk_div_phase\rev_1\verif
Example-4-14\clk_div_phase\sim\work
Example-4-17\asyn_rst\rev_1\syntmp
Example-4-17\syn_rst\rev_2\par_1
Example-4-17\syn_rst\rev_2\syntmp
Example-4-20\case\PrecisionRTL\case_impl_1
Example-4-20\case\SynplifyPro\rev_2
Example-4-20\decode\case\decode_case_impl_1
Example-4-20\decode\case\rev_1
Example-4-20\decode\if_mult\precision_impl_1
Example-4-20\decode\if_mult\rev_2
Example-4-20\decode\if_single\precision_impl_1
Example-4-20\decode\if_single\rev_1
Example-4-20\if_mult\Latch_if_mult\rev_2
Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1
Example-4-20\if_mult\SynplifyPro\rev_1
Example-4-20\if_single\PrecisionRTL\if_single_impl_1
Example-4-20\if_single\SynplifyPro\rev_2
Example-4-21\asyn_bad\rev_1\syntmp
Example-4-21\oe_edge\rev_2\syntmp
Example-4-21\syn_wr\rev_1\syntmp
Example-5-1\after_optimized\rev_2\syntmp
Example-5-1\before_optimized\rev_1\syntmp
Example-6-1\FSM\state1\rev_1
Example-6-1\FSM\state2\rev_1
Example-6-1\FSM\state3\rev_2
Example-6-1\FSM\state_default\rev_2
Example-4-1\rev_1\par_1
Example-4-1\rev_1\syntmp
Example-4-4\rev_2\par_1
Example-4-4\rev_2\syntmp
Example-4-4\rev_2\verif
Example-4-7\rev_2\par_1
Example-4-7\rev_2\syntmp
Example-4-7\sim\work
Example-4-8\rev_2\syntmp
Example-4-8\sim\work
Example-4-10\bibus\rev_1
Example-4-10\complex_bibus\rev_1
Example-4-11\rev_1\syntmp
Example-4-11\rev_1\verif
Example-4-13\ram_basic\rev_2
Example-4-13\sim\work
Example-4-14\clk_3div\sim
Example-4-14\clk_3div\synthesis
Example-4-14\clk_div_phase\rev_1
Example-4-14\clk_div_phase\sim
Example-4-16\rev_1\par_1
Example-4-16\rev_1\syntmp
Example-4-16\rev_1\verif
Example-4-17\asyn_rst\rev_1
Example-4-17\syn_rst\rev_2
Example-4-17\syn_rst\sim
Example-4-20\case\PrecisionRTL
Example-4-20\case\SynplifyPro
Example-4-20\decode\case
Example-4-20\decode\if_mult
Example-4-20\decode\if_single
Example-4-20\if_mult\Latch_if_mult
Example-4-20\if_mult\PrecisionRTL
Example-4-20\if_mult\SynplifyPro
Example-4-20\if_single\PrecisionRTL
Example-4-20\if_single\SynplifyPro
Example-4-21\asyn_bad\rev_1
Example-4-21\oe_edge\rev_2
Example-4-21\syn_wr\rev_1
Example-5-1\after_optimized\rev_2
Example-5-1\before_optimized\rev_1
Example-5-1\soure\after_optimized
Example-5-1\soure\before_optimized
Example-5-5\rev_2\par_1
Example-5-5\rev_2\syntmp
Example-5-5\rev_2\verif
Example-5-6\rev_1\syntmp
Example-5-6\rev_1\verif
Example-5-7\rev_1\par_1
Example-5-7\rev_1\syntmp
Example-5-8\rev_2\syntmp
Example-5-8\rev_2\verif
Example-6-1\FSM\state1
Example-6-1\FSM\state2
Example-6-1\FSM\state3
Example-6-1\FSM\state_default
Example-4-1\rev_1
Example-4-1\source
Example-4-4\rev_2
Example-4-4\sim
Example-4-4\source
Example-4-7\rev_2
Example-4-7\sim
Example-4-7\source
Example-4-8\rev_2
Example-4-8\sim
Example-4-8\source
Example-4-10\bibus
Example-4-10\complex_bibus
Example-4-10\source
Example-4-11\rev_1
Example-4-11\source
Example-4-13\ram_basic
Example-4-13\sim
Example-4-13\source
Example-4-14\clk_3div
Example-4-14\clk_div_phase
Example-4-14\source
Example-4-16\rev_1
Example-4-16\source
Example-4-17\asyn_rst
Example-4-17\asyn_rst_syn_release
Example-4-17\source
Example-4-17\syn_rst
Example-4-20\case
Example-4-20\decode
Example-4-20\if_mult
Example-4-20\if_single
Example-4-21\asyn_bad
Example-4-21\oe_edge
Example-4-21\syn_wr
Example-5-1\after_optimized
Example-5-1\before_optimized
Example-5-1\soure
Example-5-5\rev_2
Example-5-5\source
Example-5-6\rev_1
Example-5-6\source
Example-5-7\rev_1
Example-5-7\source
Example-5-8\rev_2
Example-5-8\source
Example-6-1\FSM
Example-7-1\Proj
Example-7-2\Proj
Example-7-3\Proj
Example-7-4\Proj
Example-8-1\sim
Example-8-2\Blocking_LHS_Delay
Example-8-2\Blocking_RHS_Delay
Example-8-2\NonBlocking_LHS_Delay
Example-8-2\NonBlocking_RHS_Delay
Example-2-1
Example-3-1
Example-3-2
Example-3-3
Example-4-1
Example-4-4
Example-4-7
Example-4-8
Example-4-10
Example-4-11
Example-4-13
Example-4-14
Example-4-16
Example-4-17
Example-4-20
Example-4-21
Example-5-1
Example-5-5
Example-5-6
Example-5-7
Example-5-8
Example-6-1
Example-7-1
Example-7-2
Example-7-3
Example-7-4
Example-8-1
Example-8-2