文件名称:Design_and_Test_VerilogHDL

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [WORD]
  • 上传时间:
  • 2012-11-26
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  • 1.8mb
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  • Z*
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Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码,很多使用的实例,并有说明,是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information.
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下载文件列表

Example-2-1

...........\HelloVlog.v

Example-3-1

...........\FullAdd.v

...........\transcript

Example-3-2

...........\FullAdd.v

Example-3-3

...........\CRC10.v

Example-4-1

...........\cnt.prd

...........\cnt.prj

...........\rev_1

...........\.....\cnt1.edf

...........\.....\cnt1.fse

...........\.....\cnt1.srm

...........\.....\cnt1.srr

...........\.....\cnt1.srs

...........\.....\cnt1.tlg

...........\.....\cnt2.edf

...........\.....\cnt2.fse

...........\.....\cnt2.srm

...........\.....\cnt2.srr

...........\.....\cnt2.srs

...........\.....\cnt2.tlg

...........\.....\cnt3.edf

...........\.....\cnt3.fse

...........\.....\cnt3.srm

...........\.....\cnt3.srr

...........\.....\cnt3.srs

...........\.....\cnt3.tlg

...........\.....\par_1

...........\.....\syntmp

...........\.....\......\cnt1.plg

...........\.....\......\cnt2.msg

...........\.....\......\cnt2.plg

...........\.....\......\cnt3.msg

...........\.....\......\cnt3.plg

...........\source

...........\......\cnt1.v

...........\......\cnt2.v

...........\......\cnt3.v

...........\......\syntmp.msg

...........\示例说明.doc

Example-4-10

............\bibus

............\.....\bibus.prd

............\.....\bibus.prj

............\.....\bibus.v

............\.....\decode.v

............\.....\rev_1

............\.....\.....\bibus.fse

............\.....\.....\bibus.srd

............\.....\.....\bibus.srm

............\.....\.....\bibus.srr

............\.....\.....\bibus.srs

............\.....\.....\bibus.sxr

............\.....\.....\bibus.tcl

............\.....\.....\bibus.tlg

............\.....\.....\bibus.vqm

............\.....\.....\bibus.xrf

............\.....\.....\bibus_cons.tcl

............\.....\.....\bibus_rm.tcl

............\.....\.....\rpt_bibus.areasrr

............\.....\.....\rpt_bibus_areasrr.htm

............\.....\.....\syntmp

............\.....\.....\......\bibus.msg

............\.....\.....\......\bibus.plg

............\.....\.....\......\bibus_cons_ui.tcl

............\.....\.....\verif

............\.....\.....\.....\bibus.vif

............\.....\syntmp.msg

............\complex_bibus

............\.............\complex_bibus.prd

............\.............\complex_bibus.prj

............\.............\complex_bibus.v

............\.............\complex_bibus2.v

............\.............\counter.v

............\.............\decode.v

............\.............\rev_1

............\.............\.....\AutoConstraint_complex_bibus.sdc

............\.............\.....\complex_bibus.fse

............\.............\.....\complex_bibus.srd

............\.............\.....\complex_bibus.srm

............\.............\.....\complex_bibus.srr

............\.............\.....\complex_bibus.srs

............\.............\.....\complex_bibus.sxr

............\.............\.....\complex_bibus.tcl

............\.............\.....\complex_bibus.tlg

............\.............\.....\complex_bibus.vqm

............\.............\.....\complex_bibus.xrf

............\.............\.....\complex_bibus2.fse

............\.............\.....\complex_bibus2.srd

............\.............\.....\complex_bibus2.srm

............\.............\.....\complex_bibus2.srr

............\.............\.....\complex_bibus2.srs

............\.............\.....\complex_bibus2.sxr

............\.............\.....\complex_bibus2.tcl

............\.............\.....\complex_bibus2.tlg

............\.............\.....\complex_bibus2.vqm

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