压缩包 : 9927429s7_uart.rar 列表
S7_UART
S7_UART\Doc
S7_UART\Doc\sscom.ini
S7_UART\Doc\sscom32.exe
S7_UART\Doc\UART控制器设计说明.doc
S7_UART\Doc\xapp341.pdf
S7_UART\func_sim
S7_UART\func_sim\rcvr.v
S7_UART\func_sim\transcript
S7_UART\func_sim\txmit.v
S7_UART\func_sim\txmit_tf.do
S7_UART\func_sim\uart.cr.mti
S7_UART\func_sim\uart.mpf
S7_UART\func_sim\uart.v
S7_UART\func_sim\uart_if.v
S7_UART\func_sim\uart_tb.do
S7_UART\func_sim\uart_tb.v
S7_UART\func_sim\uart_tb_fixed.do
S7_UART\func_sim\vish_stacktrace.vstf
S7_UART\func_sim\vsim.wlf
S7_UART\func_sim\wave.do
S7_UART\func_sim\work
S7_UART\func_sim\work\@u@a@r@t_tb
S7_UART\func_sim\work\@u@a@r@t_tb\verilog.asm
S7_UART\func_sim\work\@u@a@r@t_tb\_primary.dat
S7_UART\func_sim\work\@u@a@r@t_tb\_primary.vhd
S7_UART\func_sim\work\rcvr
S7_UART\func_sim\work\rcvr\verilog.asm
S7_UART\func_sim\work\rcvr\_primary.dat
S7_UART\func_sim\work\rcvr\_primary.vhd
S7_UART\func_sim\work\txmit
S7_UART\func_sim\work\txmit\verilog.asm
S7_UART\func_sim\work\txmit\_primary.dat
S7_UART\func_sim\work\txmit\_primary.vhd
S7_UART\func_sim\work\uart
S7_UART\func_sim\work\uart\verilog.asm
S7_UART\func_sim\work\uart\_primary.dat
S7_UART\func_sim\work\uart\_primary.vhd
S7_UART\func_sim\work\uart_if
S7_UART\func_sim\work\uart_if\verilog.asm
S7_UART\func_sim\work\uart_if\_primary.dat
S7_UART\func_sim\work\uart_if\_primary.vhd
S7_UART\func_sim\work\_info
S7_UART\physical
S7_UART\physical\altclklock0.bsf
S7_UART\physical\altclklock0.v
S7_UART\physical\altclklock0_bb.v
S7_UART\physical\async_transmitter.bsf
S7_UART\physical\cmp_state.ini
S7_UART\physical\db
S7_UART\physical\db\altsyncram_2dq.tdf
S7_UART\physical\db\altsyncram_8tj.tdf
S7_UART\physical\db\altsyncram_9un.tdf
S7_UART\physical\db\altsyncram_g5q.tdf
S7_UART\physical\db\cntr_cs6.tdf
S7_UART\physical\db\cntr_gs6.tdf
S7_UART\physical\db\cntr_ub7.tdf
S7_UART\physical\db\cntr_vt6.tdf
S7_UART\physical\db\uart_if(0).cnf.cdb
S7_UART\physical\db\uart_if(0).cnf.hdb
S7_UART\physical\db\uart_if(1).cnf.cdb
S7_UART\physical\db\uart_if(1).cnf.hdb
S7_UART\physical\db\uart_if(2).cnf.cdb
S7_UART\physical\db\uart_if(2).cnf.hdb
S7_UART\physical\db\uart_if(3).cnf.cdb
S7_UART\physical\db\uart_if(3).cnf.hdb
S7_UART\physical\db\uart_if(4).cnf.cdb
S7_UART\physical\db\uart_if(4).cnf.hdb
S7_UART\physical\db\uart_if(5).cnf.cdb
S7_UART\physical\db\uart_if(5).cnf.hdb
S7_UART\physical\db\uart_if(6).cnf.cdb
S7_UART\physical\db\uart_if(6).cnf.hdb
S7_UART\physical\db\uart_if(7).cnf.cdb
S7_UART\physical\db\uart_if(7).cnf.hdb
S7_UART\physical\db\uart_if(8).cnf.cdb
S7_UART\physical\db\uart_if(8).cnf.hdb
S7_UART\physical\db\uart_if(9).cnf.cdb
S7_UART\physical\db\uart_if(9).cnf.hdb
S7_UART\physical\db\uart_if.(0).cnf.cdb
S7_UART\physical\db\uart_if.(0).cnf.hdb
S7_UART\physical\db\uart_if.(1).cnf.cdb
S7_UART\physical\db\uart_if.(1).cnf.hdb
S7_UART\physical\db\uart_if.(2).cnf.cdb
S7_UART\physical\db\uart_if.(2).cnf.hdb
S7_UART\physical\db\uart_if.(3).cnf.cdb
S7_UART\physical\db\uart_if.(3).cnf.hdb
S7_UART\physical\db\uart_if.(4).cnf.cdb
S7_UART\physical\db\uart_if.(4).cnf.hdb
S7_UART\physical\db\uart_if.(5).cnf.cdb
S7_UART\physical\db\uart_if.(5).cnf.hdb
S7_UART\physical\db\uart_if.(6).cnf.cdb
S7_UART\physical\db\uart_if.(6).cnf.hdb
S7_UART\physical\db\uart_if.(7).cnf.cdb
S7_UART\physical\db\uart_if.(7).cnf.hdb
S7_UART\physical\db\uart_if.(8).cnf.cdb
S7_UART\physical\db\uart_if.(8).cnf.hdb
S7_UART\physical\db\uart_if.(9).cnf.cdb
S7_UART\physical\db\uart_if.(9).cnf.hdb
S7_UART\physical\db\uart_if.asm.qmsg
S7_UART\physical\db\uart_if.asm_labs.ddb
S7_UART\physical\db\uart_if.cbx.xml
S7_UART\physical\db\uart_if.cmp.cdb
S7_UART\physical\db\uart_if.cmp.hdb
S7_UART\physical\db\uart_if.cmp.logdb
S7_UART\physical\db\uart_if.cmp.rdb
S7_UART\physical\db\uart_if.cmp.tdb
S7_UART\physical\db\uart_if.cmp0.ddb
S7_UART\physical\db\uart_if.cmp2.ddb
S7_UART\physical\db\uart_if.db_info
S7_UART\physical\db\uart_if.eco.cdb
S7_UART\physical\db\uart_if.eda.qmsg
S7_UART\physical\db\uart_if.fit.qmsg
S7_UART\physical\db\uart_if.hier_info
S7_UART\physical\db\uart_if.hif
S7_UART\physical\db\uart_if.map.cdb
S7_UART\physical\db\uart_if.map.hdb
S7_UART\physical\db\uart_if.map.logdb
S7_UART\physical\db\uart_if.map.qmsg
S7_UART\physical\db\uart_if.pre_map.cdb
S7_UART\physical\db\uart_if.pre_map.hdb
S7_UART\physical\db\uart_if.psp
S7_UART\physical\db\uart_if.rtlv.hdb
S7_UART\physical\db\uart_if.rtlv_sg.cdb
S7_UART\physical\db\uart_if.rtlv_sg_swap.cdb
S7_UART\physical\db\uart_if.sgdiff.cdb
S7_UART\physical\db\uart_if.sgdiff.hdb
S7_UART\physical\db\uart_if.signalprobe.cdb
S7_UART\physical\db\uart_if.sld_design_entry.sci
S7_UART\physical\db\uart_if.sld_design_entry_dsc.sci
S7_UART\physical\db\uart_if.syn_hier_info
S7_UART\physical\db\uart_if.tan.qmsg
S7_UART\physical\db\uart_if_cmp.qrpt
S7_UART\physical\db\uart_if_hier_info
S7_UART\physical\db\uart_if_syn_hier_info
S7_UART\physical\div.bsf
S7_UART\physical\div_2.bsf
S7_UART\physical\div_2.v
S7_UART\physical\filter.bsf
S7_UART\physical\LED_flush.bsf
S7_UART\physical\rcvr.bsf
S7_UART\physical\simulation
S7_UART\physical\simulation\modelsim
S7_UART\physical\simulation\modelsim\cyclone_atoms.v
S7_UART\physical\simulation\modelsim\uart_if.vo
S7_UART\physical\simulation\modelsim\uart_if_modelsim.xrf
S7_UART\physical\simulation\modelsim\uart_if_v.sdo
S7_UART\physical\simulation\modelsim\uart_post.cr.mti
S7_UART\physical\simulation\modelsim\uart_post.mpf
S7_UART\physical\simulation\modelsim\vsim.wlf
S7_UART\physical\simulation\modelsim\work
S7_UART\physical\simulation\modelsim\work\@p@r@i@m_@d@f@f@e
S7_UART\physical\simulation\modelsim\work\@p@r@i@m_@d@f@f@e\verilog.asm
S7_UART\physical\simulation\modelsim\work\@p@r@i@m_@d@f@f@e\_primary.dat
S7_UART\physical\simulation\modelsim\work\@p@r@i@m_@d@f@f@e\_primary.vhd
S7_UART\physical\simulation\modelsim\work\@u@a@r@t_tb
S7_UART\physical\simulation\modelsim\work\@u@a@r@t_tb\verilog.asm
S7_UART\physical\simulation\modelsim\work\@u@a@r@t_tb\_primary.dat
S7_UART\physical\simulation\modelsim\work\@u@a@r@t_tb\_primary.vhd
S7_UART\physical\simulation\modelsim\work\and1
S7_UART\physical\simulation\modelsim\work\and1\verilog.asm
S7_UART\physical\simulation\modelsim\work\and1\_primary.dat
S7_UART\physical\simulation\modelsim\work\and1\_primary.vhd
S7_UART\physical\simulation\modelsim\work\and16
S7_UART\physical\simulation\modelsim\work\and16\verilog.asm
S7_UART\physical\simulation\modelsim\work\and16\_primary.dat
S7_UART\physical\simulation\modelsim\work\and16\_primary.vhd
S7_UART\physical\simulation\modelsim\work\b17mux21
S7_UART\physical\simulation\modelsim\work\b17mux21\verilog.asm
S7_UART\physical\simulation\modelsim\work\b17mux21\_primary.dat
S7_UART\physical\simulation\modelsim\work\b17mux21\_primary.vhd
S7_UART\physical\simulation\modelsim\work\b5mux21
S7_UART\physical\simulation\modelsim\work\b5mux21\verilog.asm
S7_UART\physical\simulation\modelsim\work\b5mux21\_primary.dat
S7_UART\physical\simulation\modelsim\work\b5mux21\_primary.vhd
S7_UART\physical\simulation\modelsim\work\bmux21
S7_UART\physical\simulation\modelsim\work\bmux21\verilog.asm
S7_UART\physical\simulation\modelsim\work\bmux21\_primary.dat
S7_UART\physical\simulation\modelsim\work\bmux21\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_asmiblock
S7_UART\physical\simulation\modelsim\work\cyclone_asmiblock\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_asmiblock\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_asmiblock\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_io
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_io\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_io\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_io\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_lcell
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_lcell\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_lcell\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_asynch_lcell\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_crcblock
S7_UART\physical\simulation\modelsim\work\cyclone_crcblock\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_crcblock\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_crcblock\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_dll
S7_UART\physical\simulation\modelsim\work\cyclone_dll\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_dll\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_dll\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_io
S7_UART\physical\simulation\modelsim\work\cyclone_io\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_io\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_io\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_jtag
S7_UART\physical\simulation\modelsim\work\cyclone_jtag\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_jtag\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_jtag\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_lcell
S7_UART\physical\simulation\modelsim\work\cyclone_lcell\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_lcell\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_lcell\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_lcell_register
S7_UART\physical\simulation\modelsim\work\cyclone_lcell_register\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_lcell_register\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_lcell_register\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_pll
S7_UART\physical\simulation\modelsim\work\cyclone_pll\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_pll\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_pll\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_ram_block
S7_UART\physical\simulation\modelsim\work\cyclone_ram_block\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_ram_block\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_ram_block\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_ram_clear
S7_UART\physical\simulation\modelsim\work\cyclone_ram_clear\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_ram_clear\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_ram_clear\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_ram_internal
S7_UART\physical\simulation\modelsim\work\cyclone_ram_internal\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_ram_internal\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_ram_internal\_primary.vhd
S7_UART\physical\simulation\modelsim\work\cyclone_ram_register
S7_UART\physical\simulation\modelsim\work\cyclone_ram_register\verilog.asm
S7_UART\physical\simulation\modelsim\work\cyclone_ram_register\_primary.dat
S7_UART\physical\simulation\modelsim\work\cyclone_ram_register\_primary.vhd
S7_UART\physical\simulation\modelsim\work\dffe
S7_UART\physical\simulation\modelsim\work\dffe\verilog.asm
S7_UART\physical\simulation\modelsim\work\dffe\_primary.dat
S7_UART\physical\simulation\modelsim\work\dffe\_primary.vhd
S7_UART\physical\simulation\modelsim\work\latch
S7_UART\physical\simulation\modelsim\work\latch\verilog.asm
S7_UART\physical\simulation\modelsim\work\latch\_primary.dat
S7_UART\physical\simulation\modelsim\work\latch\_primary.vhd
S7_UART\physical\simulation\modelsim\work\mux21
S7_UART\physical\simulation\modelsim\work\mux21\verilog.asm
S7_UART\physical\simulation\modelsim\work\mux21\_primary.dat
S7_UART\physical\simulation\modelsim\work\mux21\_primary.vhd
S7_UART\physical\simulation\modelsim\work\mux41
S7_UART\physical\simulation\modelsim\work\mux41\verilog.asm
S7_UART\physical\simulation\modelsim\work\mux41\_primary.dat
S7_UART\physical\simulation\modelsim\work\mux41\_primary.vhd
S7_UART\physical\simulation\modelsim\work\m_cntr
S7_UART\physical\simulation\modelsim\work\m_cntr\verilog.asm
S7_UART\physical\simulation\modelsim\work\m_cntr\_primary.dat
S7_UART\physical\simulation\modelsim\work\m_cntr\_primary.vhd
S7_UART\physical\simulation\modelsim\work\nmux21
S7_UART\physical\simulation\modelsim\work\nmux21\verilog.asm
S7_UART\physical\simulation\modelsim\work\nmux21\_primary.dat
S7_UART\physical\simulation\modelsim\work\nmux21\_primary.vhd
S7_UART\physical\simulation\modelsim\work\n_cntr
S7_UART\physical\simulation\modelsim\work\n_cntr\verilog.asm
S7_UART\physical\simulation\modelsim\work\n_cntr\_primary.dat
S7_UART\physical\simulation\modelsim\work\n_cntr\_primary.vhd
S7_UART\physical\simulation\modelsim\work\pll_reg
S7_UART\physical\simulation\modelsim\work\pll_reg\verilog.asm
S7_UART\physical\simulation\modelsim\work\pll_reg\_primary.dat
S7_UART\physical\simulation\modelsim\work\pll_reg\_primary.vhd
S7_UART\physical\simulation\modelsim\work\rcvr
S7_UART\physical\simulation\modelsim\work\rcvr\verilog.asm
S7_UART\physical\simulation\modelsim\work\rcvr\_primary.dat
S7_UART\physical\simulation\modelsim\work\rcvr\_primary.vhd
S7_UART\physical\simulation\modelsim\work\scale_cntr
S7_UART\physical\simulation\modelsim\work\scale_cntr\verilog.asm
S7_UART\physical\simulation\modelsim\work\scale_cntr\_primary.dat
S7_UART\physical\simulation\modelsim\work\scale_cntr\_primary.vhd
S7_UART\physical\simulation\modelsim\work\txmit
S7_UART\physical\simulation\modelsim\work\txmit\verilog.asm
S7_UART\physical\simulation\modelsim\work\txmit\_primary.dat
S7_UART\physical\simulation\modelsim\work\txmit\_primary.vhd
S7_UART\physical\simulation\modelsim\work\uart
S7_UART\physical\simulation\modelsim\work\uart\verilog.asm
S7_UART\physical\simulation\modelsim\work\uart\_primary.dat
S7_UART\physical\simulation\modelsim\work\uart\_primary.vhd
S7_UART\physical\simulation\modelsim\work\uart_if
S7_UART\physical\simulation\modelsim\work\uart_if\verilog.asm
S7_UART\physical\simulation\modelsim\work\uart_if\_primary.dat
S7_UART\physical\simulation\modelsim\work\uart_if\_primary.vhd
S7_UART\physical\simulation\modelsim\work\_info
S7_UART\physical\txmit.bsf
S7_UART\physical\uart.bsf
S7_UART\physical\uart_if.asm.rpt
S7_UART\physical\uart_if.bsf
S7_UART\physical\uart_if.cdf
S7_UART\physical\uart_if.done
S7_UART\physical\uart_if.eda.rpt
S7_UART\physical\uart_if.fit.eqn
S7_UART\physical\uart_if.fit.rpt
S7_UART\physical\uart_if.fit.summary
S7_UART\physical\uart_if.fld
S7_UART\physical\uart_if.flow.rpt
S7_UART\physical\uart_if.map.eqn
S7_UART\physical\uart_if.map.rpt
S7_UART\physical\uart_if.map.summary
S7_UART\physical\uart_if.pin
S7_UART\physical\uart_if.pof
S7_UART\physical\uart_if.qpf
S7_UART\physical\uart_if.qsf
S7_UART\physical\uart_if.qws
S7_UART\physical\uart_if.sim.rpt
S7_UART\physical\uart_if.sof
S7_UART\physical\uart_if.tan.rpt
S7_UART\physical\uart_if.tan.summary
S7_UART\physical\uart_if_assignment_defaults.qdf
S7_UART\physical\uart_if_description.txt
S7_UART\physical\uart_if_rom.bdf
S7_UART\physical\uart_rom.bsf
S7_UART\physical\uart_rom.mif
S7_UART\physical\uart_rom.v
S7_UART\physical\uart_rom_bb.v
S7_UART\physical\undo_redo.txt
S7_UART\physical\vga.vhd
S7_UART\physical\vga_vl.bsf
S7_UART\Src
S7_UART\Src\div1_8m.v
S7_UART\Src\filter.v
S7_UART\Src\rcvr.v
S7_UART\Src\rcvr_tf.v
S7_UART\Src\txmit.v
S7_UART\Src\txmit_tf.v
S7_UART\Src\uart.v
S7_UART\Src\uart_if.v
S7_UART\Src\uart_if_fixed.v
S7_UART\Src\uart_tb.v
S7_UART\sythesis
S7_UART\sythesis\db
S7_UART\sythesis\lec
S7_UART\sythesis\lec\uart_if.vlc
S7_UART\sythesis\lec\uart_if.vmc
S7_UART\sythesis\lec\uart_if.vsc
S7_UART\sythesis\rpt_uart_if.areasrr
S7_UART\sythesis\syntmp
S7_UART\sythesis\syntmp\uart_if.plg
S7_UART\sythesis\UART.prd
S7_UART\sythesis\UART.prj
S7_UART\sythesis\uart_if.fse
S7_UART\sythesis\uart_if.srd
S7_UART\sythesis\uart_if.srm
S7_UART\sythesis\uart_if.srr
S7_UART\sythesis\uart_if.srs
S7_UART\sythesis\uart_if.sxr
S7_UART\sythesis\uart_if.tcl
S7_UART\sythesis\uart_if.tlg
S7_UART\sythesis\uart_if.vqm
S7_UART\sythesis\uart_if.vtc
S7_UART\sythesis\uart_if.xrf
S7_UART\sythesis\uart_if_cons.tcl
S7_UART\sythesis\uart_if_rm.tcl
S7_UART\sythesis\verif
S7_UART\sythesis\verif\uart_if.vif