文件名称:S7_UART
介绍说明－－下载内容均来自于网络，请自行研究使用
利用FPGA实现串口通信，很好的学习资料
尤其是对 verilog不熟的朋友
尤其是对 verilog不熟的朋友
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压缩包 : 29782162s7_uart.rar 列表 S7_UART\physical\.sopc_builder\install.ptf S7_UART\physical\.sopc_builder S7_UART\physical\db\wed.zsf S7_UART\physical\db\uart_if_rom.db_info S7_UART\physical\db\altsyncram_lv61.tdf S7_UART\physical\db\uart_if_rom.sld_design_entry_dsc.sci S7_UART\physical\db\uart_if_rom.(0).cnf.cdb S7_UART\physical\db\uart_if_rom.(1).cnf.cdb S7_UART\physical\db\uart_if_rom.(1).cnf.hdb S7_UART\physical\db\uart_if_rom.(2).cnf.cdb S7_UART\physical\db\uart_if_rom.(2).cnf.hdb S7_UART\physical\db\uart_if_rom.(3).cnf.cdb S7_UART\physical\db\uart_if_rom.(3).cnf.hdb S7_UART\physical\db\uart_if_rom.(4).cnf.cdb S7_UART\physical\db\uart_if_rom.(4).cnf.hdb S7_UART\physical\db\uart_if_rom.(5).cnf.cdb S7_UART\physical\db\uart_if_rom.(5).cnf.hdb S7_UART\physical\db\uart_if_rom.(6).cnf.cdb S7_UART\physical\db\uart_if_rom.(6).cnf.hdb S7_UART\physical\db\uart_if_rom.cbx.xml S7_UART\physical\db\uart_if_rom.hif S7_UART\physical\db\uart_if_rom.(7).cnf.cdb S7_UART\physical\db\uart_if_rom.(7).cnf.hdb S7_UART\physical\db\uart_if_rom.cmp.kpt S7_UART\physical\db\uart_if_rom.(8).cnf.cdb S7_UART\physical\db\uart_if_rom.(8).cnf.hdb S7_UART\physical\db\uart_if_rom.map.qmsg S7_UART\physical\db\uart_if_rom.fit.qmsg S7_UART\physical\db\uart_if_rom.hier_info S7_UART\physical\db\uart_if_rom.(0).cnf.hdb S7_UART\physical\db\uart_if_rom.cmp.logdb S7_UART\physical\db\uart_if_rom.(9).cnf.cdb S7_UART\physical\db\uart_if_rom.(9).cnf.hdb S7_UART\physical\db\uart_if_rom.pre_map.hdb S7_UART\physical\db\uart_if_rom.rtlv_sg.cdb S7_UART\physical\db\uart_if_rom.rtlv_sg_swap.cdb S7_UART\physical\db\uart_if_rom.psp S7_UART\physical\db\uart_if_rom.pre_map.cdb S7_UART\physical\db\uart_if_rom.map.cdb S7_UART\physical\db\uart_if_rom.dbp S7_UART\physical\db\uart_if_rom.rtlv.hdb S7_UART\physical\db\uart_if_rom.map.logdb S7_UART\physical\db\uart_if_rom.sgdiff.hdb S7_UART\physical\db\uart_if_rom.syn_hier_info S7_UART\physical\db\uart_if_rom.sgdiff.cdb S7_UART\physical\db\uart_if_rom.asm.qmsg S7_UART\physical\db\uart_if_rom.map.hdb S7_UART\physical\db\uart_if_rom.tan.qmsg S7_UART\physical\db\uart_if_rom.sim.qmsg S7_UART\physical\db\uart_if_rom.eda.qmsg S7_UART\physical\db\uart_if_rom.fnsim.qmsg S7_UART\physical\db\uart_if_rom.cmp.cdb S7_UART\physical\db\uart_if_rom.signalprobe.cdb S7_UART\physical\db\uart_if_rom.cmp2.ddb S7_UART\physical\db\uart_if_rom.cmp.hdb S7_UART\physical\db\uart_if_rom.cmp.rdb S7_UART\physical\db\uart_if_rom.sim.hdb S7_UART\physical\db\uart_if_rom.sim.rdb S7_UART\physical\db\uart_if_rom.fnsim.cdb S7_UART\physical\db\uart_if_rom.fnsim.hdb S7_UART\physical\db\uart_if_rom.cdb.qmsg S7_UART\physical\db\uart_if_rom.sld_design_entry.sci S7_UART\physical\db\uart_if_rom.eco.cdb S7_UART\physical\db S7_UART\physical\div.bsf S7_UART\physical\div.v S7_UART\physical\filter.bsf S7_UART\physical\filter.v S7_UART\physical\rcvr.bsf S7_UART\physical\sopc_builder_debug_log.txt S7_UART\physical\txmit.bsf S7_UART\physical\uart.bsf S7_UART\physical\uart_if.bsf S7_UART\physical\uart_if.v S7_UART\physical\uart_if_rom.bdf S7_UART\physical\uart_if_rom.done S7_UART\physical\uart_if_rom.dpf S7_UART\physical\uart_if_rom.flow.rpt S7_UART\physical\uart_if_rom.map.rpt S7_UART\physical\uart_if_rom.map.summary S7_UART\physical\uart_if_rom.mif S7_UART\physical\uart_if_rom.qpf S7_UART\physical\uart_if_rom.qsf S7_UART\physical\uart_if_rom.qws S7_UART\physical\uart_if_rom.v S7_UART\physical\uart_rom.bsf S7_UART\physical\uart_rom.inc S7_UART\physical\uart_rom.tdf S7_UART\physical\uart_rom.v S7_UART\physical\uart_rom_bb.v S7_UART\physical\uart_rom.mif S7_UART\physical\uart_if_rom.pin S7_UART\physical\uart_if_rom.fit.rpt S7_UART\physical\uart_if_rom.fit.smsg S7_UART\physical\uart_if_rom.fit.summary S7_UART\physical\uart_if_rom.sof S7_UART\physical\uart_if_rom.pof S7_UART\physical\uart_if_rom.asm.rpt S7_UART\physical\uart_if_rom.tan.summary S7_UART\physical\uart_if_rom.tan.rpt S7_UART\physical\simulation\modelsim\uart\work\_info S7_UART\physical\simulation\modelsim\uart\work\uart\_primary.vhd S7_UART\physical\simulation\modelsim\uart\work\uart\verilog.asm S7_UART\physical\simulation\modelsim\uart\work\uart\_primary.dat S7_UART\physical\simulation\modelsim\uart\work\uart S7_UART\physical\simulation\modelsim\uart\work\@u@a@r@t_tb\_primary.vhd S7_UART\physical\simulation\modelsim\uart\work\@u@a@r@t_tb\verilog.asm S7_UART\physical\simulation\modelsim\uart\work\@u@a@r@t_tb\_primary.dat S7_UART\physical\simulation\modelsim\uart\work\@u@a@r@t_tb S7_UART\physical\simulation\modelsim\uart\work S7_UART\physical\simulation\modelsim\uart\uart.mpf S7_UART\physical\simulation\modelsim\uart\uart.cr.mti S7_UART\physical\simulation\modelsim\uart S7_UART\physical\simulation\modelsim S7_UART\physical\simulation S7_UART\physical\uart_if_rom.eda.rpt S7_UART\physical\uart_if_rom.cdf S7_UART\physical\uart_if_rom.vwf S7_UART\physical\uart_if_rom.sim.rpt S7_UART\physical S7_UART\sythesis\rpt_uart_if.areasrr S7_UART\sythesis\UART.prd S7_UART\sythesis\UART.prj S7_UART\sythesis\uart_if.fse S7_UART\sythesis\uart_if.srd S7_UART\sythesis\uart_if.srm S7_UART\sythesis\uart_if.srr S7_UART\sythesis\uart_if.srs S7_UART\sythesis\uart_if.sxr S7_UART\sythesis\uart_if.tcl S7_UART\sythesis\uart_if.tlg S7_UART\sythesis\uart_if.vqm S7_UART\sythesis\uart_if.vtc S7_UART\sythesis\uart_if.xrf S7_UART\sythesis\uart_if_cons.tcl S7_UART\sythesis\uart_if_rm.tcl S7_UART\sythesis\db S7_UART\sythesis\verif\uart_if.vif S7_UART\sythesis\verif S7_UART\sythesis\syntmp\uart_if.plg S7_UART\sythesis\syntmp S7_UART\sythesis\lec\uart_if.vlc S7_UART\sythesis\lec\uart_if.vmc S7_UART\sythesis\lec\uart_if.vsc S7_UART\sythesis\lec S7_UART\sythesis\uart_rom.mif S7_UART\sythesis S7_UART