文件名称:fpga_fifo_0122_02
- 所属分类：
- 其它资源
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2008-10-13
- 文件大小：
- 2.22mb
- 下载次数：
- 0次
- 提 供 者：
- zhouh*****
- 相关连接：
- 无
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可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序
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压缩包 : 59564372fpga_fifo_0122_02.rar 列表 fpga_fifo_0122_02\smartgen\clk_pll\clk_pll.cxf fpga_fifo_0122_02\smartgen\clk_pll\clk_pll.gen fpga_fifo_0122_02\smartgen\clk_pll\clk_pll.log fpga_fifo_0122_02\smartgen\clk_pll\clk_pll.v fpga_fifo_0122_02\smartgen\clk_pll fpga_fifo_0122_02\smartgen\clk_pll_work.ixf fpga_fifo_0122_02\smartgen\fifo_fpga\fifo_fpga.shx fpga_fifo_0122_02\smartgen\fifo_fpga\fifo_fpga_R0C0.mem fpga_fifo_0122_02\smartgen\fifo_fpga\fifo_fpga_R1C0.mem fpga_fifo_0122_02\smartgen\fifo_fpga\fifo_fpga_R2C0.mem fpga_fifo_0122_02\smartgen\fifo_fpga fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.cxf fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.gen fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.log fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v fpga_fifo_0122_02\smartgen\fifo_fpga1280x8 fpga_fifo_0122_02\smartgen\fifo_fpga1280x8_work.ixf fpga_fifo_0122_02\smartgen\smartgen.aws fpga_fifo_0122_02\smartgen fpga_fifo_0122_02\stimulus\BtimErrors.log fpga_fifo_0122_02\stimulus\ctr_data_tb.v fpga_fifo_0122_02\stimulus\ctr_data_tb.v.bak fpga_fifo_0122_02\stimulus\files_to_build.txt fpga_fifo_0122_02\stimulus\fpga_core.dsk fpga_fifo_0122_02\stimulus\fpga_core.hpj fpga_fifo_0122_02\stimulus\fpga_core_tb.v fpga_fifo_0122_02\stimulus\fpga_core_tb.v.bak fpga_fifo_0122_02\stimulus\waveperl.log fpga_fifo_0122_02\stimulus\fifo_fpga_1280x8_tb.v fpga_fifo_0122_02\stimulus fpga_fifo_0122_02\synthesis\backup\fpga_core.srr fpga_fifo_0122_02\synthesis\backup fpga_fifo_0122_02\synthesis\fpga_core.areasrr fpga_fifo_0122_02\synthesis\fpga_core.edn fpga_fifo_0122_02\synthesis\fpga_core.map fpga_fifo_0122_02\synthesis\fpga_core.sdf fpga_fifo_0122_02\synthesis\fpga_core.srd fpga_fifo_0122_02\synthesis\fpga_core.srm fpga_fifo_0122_02\synthesis\fpga_core.srr fpga_fifo_0122_02\synthesis\fpga_core.tlg fpga_fifo_0122_02\synthesis\fpga_core_sdc.sdc fpga_fifo_0122_02\synthesis\run_options.txt fpga_fifo_0122_02\synthesis\stdout.log fpga_fifo_0122_02\synthesis\syntmp\fpga_core.msg fpga_fifo_0122_02\synthesis\syntmp\fpga_core.plg fpga_fifo_0122_02\synthesis\syntmp fpga_fifo_0122_02\synthesis\fpga_core.srs fpga_fifo_0122_02\synthesis\traplog.tlg fpga_fifo_0122_02\synthesis\.recordref fpga_fifo_0122_02\synthesis\fpga_core_syn.prj fpga_fifo_0122_02\synthesis fpga_fifo_0122_02\viewdraw\vf\project.lst fpga_fifo_0122_02\viewdraw\vf fpga_fifo_0122_02\viewdraw\sch fpga_fifo_0122_02\viewdraw\sym fpga_fifo_0122_02\viewdraw\wir fpga_fifo_0122_02\viewdraw\viewdraw.ini fpga_fifo_0122_02\viewdraw fpga_fifo_0122_02\new.prj fpga_fifo_0122_02\designer\impl2\designer_genhdl.log fpga_fifo_0122_02\designer\impl2\fpga_core.tcl fpga_fifo_0122_02\designer\impl2\simulation fpga_fifo_0122_02\designer\impl2 fpga_fifo_0122_02\designer\impl1\simulation fpga_fifo_0122_02\designer\impl1 fpga_fifo_0122_02\designer fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v.bak fpga_fifo_0122_02\hdl fpga_fifo_0122_02\simulation\fifo_fpga_R0C0.mem fpga_fifo_0122_02\simulation\fifo_fpga_R1C0.mem fpga_fifo_0122_02\simulation\fifo_fpga_R2C0.mem fpga_fifo_0122_02\simulation\rec_data.dat fpga_fifo_0122_02\simulation\modelsim.ini.sav fpga_fifo_0122_02\simulation\modelsim.ini fpga_fifo_0122_02\simulation\modelsim.log fpga_fifo_0122_02\simulation\presynth\ctr_data_tb\verilog.psm fpga_fifo_0122_02\simulation\presynth\ctr_data_tb\_primary.vhd fpga_fifo_0122_02\simulation\presynth\ctr_data_tb\_primary.dat fpga_fifo_0122_02\simulation\presynth\ctr_data_tb fpga_fifo_0122_02\simulation\presynth\fifo_fpga\verilog.psm fpga_fifo_0122_02\simulation\presynth\fifo_fpga\_primary.dat fpga_fifo_0122_02\simulation\presynth\fifo_fpga\_primary.vhd fpga_fifo_0122_02\simulation\presynth\fifo_fpga fpga_fifo_0122_02\simulation\presynth\fifo_fpga1280x8\verilog.psm fpga_fifo_0122_02\simulation\presynth\fifo_fpga1280x8\_primary.vhd fpga_fifo_0122_02\simulation\presynth\fifo_fpga1280x8\_primary.dat fpga_fifo_0122_02\simulation\presynth\fifo_fpga1280x8 fpga_fifo_0122_02\simulation\presynth\fpga_core\verilog.psm fpga_fifo_0122_02\simulation\presynth\fpga_core\_primary.vhd fpga_fifo_0122_02\simulation\presynth\fpga_core\_primary.dat fpga_fifo_0122_02\simulation\presynth\fpga_core fpga_fifo_0122_02\simulation\presynth\fpga_core_tb\verilog.psm fpga_fifo_0122_02\simulation\presynth\fpga_core_tb\_primary.dat fpga_fifo_0122_02\simulation\presynth\fpga_core_tb\_primary.vhd fpga_fifo_0122_02\simulation\presynth\fpga_core_tb fpga_fifo_0122_02\simulation\presynth\_info fpga_fifo_0122_02\simulation\presynth\_temp fpga_fifo_0122_02\simulation\presynth\fpga_fpga_1280x8_tb\_primary.vhd fpga_fifo_0122_02\simulation\presynth\fpga_fpga_1280x8_tb\verilog.psm fpga_fifo_0122_02\simulation\presynth\fpga_fpga_1280x8_tb\_primary.dat fpga_fifo_0122_02\simulation\presynth\fpga_fpga_1280x8_tb fpga_fifo_0122_02\simulation\presynth fpga_fifo_0122_02\simulation\run.do fpga_fifo_0122_02\simulation\vsim.wlf fpga_fifo_0122_02\simulation\meminit.dat fpga_fifo_0122_02\simulation\recv_data.dat fpga_fifo_0122_02\simulation\uart_send_data.dat.bak fpga_fifo_0122_02\simulation\uart_send_data.dat fpga_fifo_0122_02\simulation fpga_fifo_0122_02\component fpga_fifo_0122_02\constraint fpga_fifo_0122_02\coreconsole fpga_fifo_0122_02\phy_synthesis fpga_fifo_0122_02