文件名称:sdram_control_burst
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精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write
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下载文件列表
test
....\ise
....\...\automake.log
....\...\coregen.log
....\...\coregen.prj
....\...\fpga.cmd_log
....\...\fpga.lso
....\...\fpga.ngc
....\...\fpga.ngr
....\...\fpga.prj
....\...\fpga.stx
....\...\fpga.syr
....\...\fpga_vhdl.prj
....\...\test.dhp
....\...\test.npl
....\...\xst
....\...\...\work
....\...\...\....\hdllib.ref
....\...\...\....\vlg22
....\...\...\....\.....\fpga.bin
....\...\__projnav
....\...\.........\coregen.rsp
....\...\.........\fpga.xst
....\...\.........\runXst_tcl.rsp
....\...\.........\test.gfl
....\...\.........\test_flowplus.gfl
....\...\__projnav.log
....\modelsim
....\........\test.cr.mti
....\........\test.mpf
....\........\vsim.wlf
....\........\wave.do
....\........\wave2.do
....\........\work
....\........\....\@v51
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\fpga
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\mt48lc1m16a1
....\........\....\............\verilog.asm
....\........\....\............\_primary.dat
....\........\....\............\_primary.vhd
....\........\....\top
....\........\....\...\verilog.asm
....\........\....\...\_primary.dat
....\........\....\...\_primary.vhd
....\........\....\_info
....\src
....\...\fpga.v
....\...\global.h
....\...\mt48lc1m16a1-8a.v
....\...\top.v
....\...\V51.v
....\ise
....\...\automake.log
....\...\coregen.log
....\...\coregen.prj
....\...\fpga.cmd_log
....\...\fpga.lso
....\...\fpga.ngc
....\...\fpga.ngr
....\...\fpga.prj
....\...\fpga.stx
....\...\fpga.syr
....\...\fpga_vhdl.prj
....\...\test.dhp
....\...\test.npl
....\...\xst
....\...\...\work
....\...\...\....\hdllib.ref
....\...\...\....\vlg22
....\...\...\....\.....\fpga.bin
....\...\__projnav
....\...\.........\coregen.rsp
....\...\.........\fpga.xst
....\...\.........\runXst_tcl.rsp
....\...\.........\test.gfl
....\...\.........\test_flowplus.gfl
....\...\__projnav.log
....\modelsim
....\........\test.cr.mti
....\........\test.mpf
....\........\vsim.wlf
....\........\wave.do
....\........\wave2.do
....\........\work
....\........\....\@v51
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\fpga
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\mt48lc1m16a1
....\........\....\............\verilog.asm
....\........\....\............\_primary.dat
....\........\....\............\_primary.vhd
....\........\....\top
....\........\....\...\verilog.asm
....\........\....\...\_primary.dat
....\........\....\...\_primary.vhd
....\........\....\_info
....\src
....\...\fpga.v
....\...\global.h
....\...\mt48lc1m16a1-8a.v
....\...\top.v
....\...\V51.v