文件名称:fft_debug
介绍说明－－下载内容均来自于网络，请自行研究使用
能进行32位浮点数fft运算的VHDL描述。-can float for 32 fft Operational VHDL descr iption.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fft_debug
.........\and_gates.vhd
.........\baseindex.vhd
.........\butter_lib.vhd
.........\but_gen.vhd
.........\control_main.vhd
.........\cont_gen.vhd
.........\counter.vhd
.........\cycles.vhd
.........\divide.vhd
.........\ioadd_gen.vhd
.........\iod_staged.vhd
.........\level_edge.vhd
.........\l_block.vhd
.........\multiply.vhd
.........\mult_clock.vhd
.........\mux.vhd
.........\mux_add.vhd
.........\negate.vhd
.........\normalize.vhd
.........\normalize.vhd.bak
.........\print_result.vhd
.........\print_result2.vhd
.........\ram_shift.vhd
.........\reg_dpram.vhd
.........\rom.vhd
.........\romadd_gen.vhd
.........\rom_ram.vhd
.........\r_block.vhd
.........\shift2.vhd
.........\stage.vhd.bak
.........\stage_gen.vhd
.........\subtractor.vhd
.........\summer.vhd
.........\swap.vhd
.........\synth_main.vhd
.........\synth_test.vhd
.........\test.cr.mti
.........\test.mpf
.........\transcript
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\work
.........\....\and_gates
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\baseindex
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\butter_lib
.........\....\..........\_primary.dat
.........\....\..........\_vhdl.asm
.........\....\but_gen
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\control_main
.........\....\............\rtl.asm
.........\....\............\rtl.dat
.........\....\............\_primary.dat
.........\....\cont_gen
.........\....\........\rtl.asm
.........\....\........\rtl.dat
.........\....\........\_primary.dat
.........\....\counter
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\cycles
.........\....\......\rtl.asm
.........\....\......\rtl.dat
.........\....\......\_primary.dat
.........\....\divide
.........\....\......\rtl.asm
.........\....\......\rtl.dat
.........\....\......\_primary.dat
.........\....\ioadd_gen
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\iod_staged
.........\....\..........\rtl.asm
.........\....\..........\rtl.dat
.........\....\..........\_primary.dat
.........\....\level_edge
.........\....\..........\rtl.asm
.........\....\..........\rtl.dat
.........\....\..........\_primary.dat
.........\....\l_block
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\multiply
.........\....\........\rtl.asm
.........\....\........\rtl.dat
.........\....\........\_primary.dat
.........\....\mult_clock
.........\....\..........\rtl.asm
.........\and_gates.vhd
.........\baseindex.vhd
.........\butter_lib.vhd
.........\but_gen.vhd
.........\control_main.vhd
.........\cont_gen.vhd
.........\counter.vhd
.........\cycles.vhd
.........\divide.vhd
.........\ioadd_gen.vhd
.........\iod_staged.vhd
.........\level_edge.vhd
.........\l_block.vhd
.........\multiply.vhd
.........\mult_clock.vhd
.........\mux.vhd
.........\mux_add.vhd
.........\negate.vhd
.........\normalize.vhd
.........\normalize.vhd.bak
.........\print_result.vhd
.........\print_result2.vhd
.........\ram_shift.vhd
.........\reg_dpram.vhd
.........\rom.vhd
.........\romadd_gen.vhd
.........\rom_ram.vhd
.........\r_block.vhd
.........\shift2.vhd
.........\stage.vhd.bak
.........\stage_gen.vhd
.........\subtractor.vhd
.........\summer.vhd
.........\swap.vhd
.........\synth_main.vhd
.........\synth_test.vhd
.........\test.cr.mti
.........\test.mpf
.........\transcript
.........\vish_stacktrace.vstf
.........\vsim.wlf
.........\work
.........\....\and_gates
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\baseindex
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\butter_lib
.........\....\..........\_primary.dat
.........\....\..........\_vhdl.asm
.........\....\but_gen
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\control_main
.........\....\............\rtl.asm
.........\....\............\rtl.dat
.........\....\............\_primary.dat
.........\....\cont_gen
.........\....\........\rtl.asm
.........\....\........\rtl.dat
.........\....\........\_primary.dat
.........\....\counter
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\cycles
.........\....\......\rtl.asm
.........\....\......\rtl.dat
.........\....\......\_primary.dat
.........\....\divide
.........\....\......\rtl.asm
.........\....\......\rtl.dat
.........\....\......\_primary.dat
.........\....\ioadd_gen
.........\....\.........\rtl.asm
.........\....\.........\rtl.dat
.........\....\.........\_primary.dat
.........\....\iod_staged
.........\....\..........\rtl.asm
.........\....\..........\rtl.dat
.........\....\..........\_primary.dat
.........\....\level_edge
.........\....\..........\rtl.asm
.........\....\..........\rtl.dat
.........\....\..........\_primary.dat
.........\....\l_block
.........\....\.......\rtl.asm
.........\....\.......\rtl.dat
.........\....\.......\_primary.dat
.........\....\multiply
.........\....\........\rtl.asm
.........\....\........\rtl.dat
.........\....\........\_primary.dat
.........\....\mult_clock
.........\....\..........\rtl.asm