文件名称:whole_clock_code

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 165kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • dan***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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一个电子中的verilog实验源代码。适合verilog初学者学习参考-an electronic experiments of Verilog source code. Suitable for beginners learning Verilog reference
(系统自动生成,下载前可以参看下载内容)

下载文件列表

my_final_clock

..............\add3.v

..............\binary_to_BCD.v

..............\clock2001.rar

..............\clock_alarm_set.v

..............\clock_scan_block.rar

..............\date_screen_set.v

..............\division.v

..............\led.v

..............\modelsim.ini

..............\my_clock.v

..............\my_clock_tb.v

..............\my_division.v

..............\o_alarm.v

..............\scan.v

..............\second.v

..............\time_screen_set.v

..............\top.v

..............\transcript

..............\vsim.wlf

..............\work

..............\....\add3

..............\....\....\verilog.asm

..............\....\....\_primary.dat

..............\....\....\_primary.vhd

..............\....\binary_to_@b@c@d

..............\....\................\verilog.asm

..............\....\................\_primary.dat

..............\....\................\_primary.vhd

..............\....\clock_alarm_set

..............\....\...............\verilog.asm

..............\....\...............\_primary.dat

..............\....\...............\_primary.vhd

..............\....\date_screen_set

..............\....\...............\verilog.asm

..............\....\...............\_primary.dat

..............\....\...............\_primary.vhd

..............\....\division

..............\....\........\verilog.asm

..............\....\........\_primary.dat

..............\....\........\_primary.vhd

..............\....\led

..............\....\...\verilog.asm

..............\....\...\_primary.dat

..............\....\...\_primary.vhd

..............\....\my_clock

..............\....\........\verilog.asm

..............\....\........\_primary.dat

..............\....\........\_primary.vhd

..............\....\my_clock_tb

..............\....\...........\verilog.asm

..............\....\...........\_primary.dat

..............\....\...........\_primary.vhd

..............\....\my_division

..............\....\...........\verilog.asm

..............\....\...........\_primary.dat

..............\....\...........\_primary.vhd

..............\....\o_alarm

..............\....\.......\verilog.asm

..............\....\.......\_primary.dat

..............\....\.......\_primary.vhd

..............\....\scan

..............\....\....\verilog.asm

..............\....\....\_primary.dat

..............\....\....\_primary.vhd

..............\....\second

..............\....\......\verilog.asm

..............\....\......\_primary.dat

..............\....\......\_primary.vhd

..............\....\time_screen_set

..............\....\...............\verilog.asm

..............\....\...............\_primary.dat

..............\....\...............\_primary.vhd

..............\....\top

..............\....\...\verilog.asm

..............\....\...\_primary.dat

..............\....\...\_primary.vhd

..............\....\_info

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