文件名称:chengxu(vhdl)
介绍说明－－下载内容均来自于网络，请自行研究使用
这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序-VHDL and FPGA prepared by the computer serial communication procedures and an LED procedures
(系统自动生成,下载前可以参看下载内容)
下载文件列表
vhdl
....\led
....\...\cmp_state.ini
....\...\control.bsf
....\...\control.vhd
....\...\db
....\...\..\top.asm.qmsg
....\...\..\top.cbx.xml
....\...\..\top.cmp.cdb
....\...\..\top.cmp.hdb
....\...\..\top.cmp.rdb
....\...\..\top.cmp.tdb
....\...\..\top.cmp0.ddb
....\...\..\top.db_info
....\...\..\top.eco.cdb
....\...\..\top.eda.qmsg
....\...\..\top.fit.qmsg
....\...\..\top.hier_info
....\...\..\top.hif
....\...\..\top.map.cdb
....\...\..\top.map.hdb
....\...\..\top.map.qmsg
....\...\..\top.pre_map.cdb
....\...\..\top.pre_map.hdb
....\...\..\top.psp
....\...\..\top.rtlv.hdb
....\...\..\top.rtlv_sg.cdb
....\...\..\top.rtlv_sg_swap.cdb
....\...\..\top.sgdiff.cdb
....\...\..\top.sgdiff.hdb
....\...\..\top.signalprobe.cdb
....\...\..\top.sld_design_entry.sci
....\...\..\top.sld_design_entry_dsc.sci
....\...\..\top.syn_hier_info
....\...\..\top.tan.qmsg
....\...\..\top_cmp.qrpt
....\...\fenpin.bsf
....\...\fenpin.vhd
....\...\simulation
....\...\..........\modelsim
....\...\..........\........\top.vo
....\...\..........\........\top_modelsim.xrf
....\...\..........\........\top_v.sdo
....\...\top.asm.rpt
....\...\top.bdf
....\...\top.cdf
....\...\top.done
....\...\top.eda.rpt
....\...\top.fit.eqn
....\...\top.fit.rpt
....\...\top.fit.summary
....\...\top.flow.rpt
....\...\top.map.eqn
....\...\top.map.rpt
....\...\top.map.summary
....\...\top.pin
....\...\top.pof
....\...\top.qpf
....\...\top.qsf
....\...\top.qws
....\...\top.sof
....\...\top.tan.rpt
....\...\top.tan.summary
....\...\undo_redo.txt
....\uart_sent
....\.........\cmp_state.ini
....\.........\db
....\.........\..\top.asm.qmsg
....\.........\..\top.cbx.xml
....\.........\..\top.cmp.cdb
....\.........\..\top.cmp.hdb
....\.........\..\top.cmp.rdb
....\.........\..\top.cmp.tdb
....\.........\..\top.cmp0.ddb
....\.........\..\top.db_info
....\.........\..\top.eco.cdb
....\.........\..\top.fit.qmsg
....\.........\..\top.hier_info
....\.........\..\top.hif
....\.........\..\top.map.cdb
....\.........\..\top.map.hdb
....\.........\..\top.map.qmsg
....\.........\..\top.pre_map.cdb
....\.........\..\top.pre_map.hdb
....\.........\..\top.psp
....\.........\..\top.rtlv.hdb
....\.........\..\top.rtlv_sg.cdb
....\.........\..\top.rtlv_sg_swap.cdb
....\.........\..\top.sgdiff.cdb
....\.........\..\top.sgdiff.hdb
....\.........\..\top.signalprobe.cdb
....\.........\..\top.sld_design_entry.sci
....\.........\..\top.sld_design_entry_dsc.sci
....\.........\..\top.syn_hier_info
....\.........\..\top.tan.qmsg
....\.........\..\top_cmp.qrpt
....\.........\fenpin_115200.bsf
....\.........\fenpin_115200.vhd
....\.........\fenpin_even.vhd
....\.........\sent.bsf
....\led
....\...\cmp_state.ini
....\...\control.bsf
....\...\control.vhd
....\...\db
....\...\..\top.asm.qmsg
....\...\..\top.cbx.xml
....\...\..\top.cmp.cdb
....\...\..\top.cmp.hdb
....\...\..\top.cmp.rdb
....\...\..\top.cmp.tdb
....\...\..\top.cmp0.ddb
....\...\..\top.db_info
....\...\..\top.eco.cdb
....\...\..\top.eda.qmsg
....\...\..\top.fit.qmsg
....\...\..\top.hier_info
....\...\..\top.hif
....\...\..\top.map.cdb
....\...\..\top.map.hdb
....\...\..\top.map.qmsg
....\...\..\top.pre_map.cdb
....\...\..\top.pre_map.hdb
....\...\..\top.psp
....\...\..\top.rtlv.hdb
....\...\..\top.rtlv_sg.cdb
....\...\..\top.rtlv_sg_swap.cdb
....\...\..\top.sgdiff.cdb
....\...\..\top.sgdiff.hdb
....\...\..\top.signalprobe.cdb
....\...\..\top.sld_design_entry.sci
....\...\..\top.sld_design_entry_dsc.sci
....\...\..\top.syn_hier_info
....\...\..\top.tan.qmsg
....\...\..\top_cmp.qrpt
....\...\fenpin.bsf
....\...\fenpin.vhd
....\...\simulation
....\...\..........\modelsim
....\...\..........\........\top.vo
....\...\..........\........\top_modelsim.xrf
....\...\..........\........\top_v.sdo
....\...\top.asm.rpt
....\...\top.bdf
....\...\top.cdf
....\...\top.done
....\...\top.eda.rpt
....\...\top.fit.eqn
....\...\top.fit.rpt
....\...\top.fit.summary
....\...\top.flow.rpt
....\...\top.map.eqn
....\...\top.map.rpt
....\...\top.map.summary
....\...\top.pin
....\...\top.pof
....\...\top.qpf
....\...\top.qsf
....\...\top.qws
....\...\top.sof
....\...\top.tan.rpt
....\...\top.tan.summary
....\...\undo_redo.txt
....\uart_sent
....\.........\cmp_state.ini
....\.........\db
....\.........\..\top.asm.qmsg
....\.........\..\top.cbx.xml
....\.........\..\top.cmp.cdb
....\.........\..\top.cmp.hdb
....\.........\..\top.cmp.rdb
....\.........\..\top.cmp.tdb
....\.........\..\top.cmp0.ddb
....\.........\..\top.db_info
....\.........\..\top.eco.cdb
....\.........\..\top.fit.qmsg
....\.........\..\top.hier_info
....\.........\..\top.hif
....\.........\..\top.map.cdb
....\.........\..\top.map.hdb
....\.........\..\top.map.qmsg
....\.........\..\top.pre_map.cdb
....\.........\..\top.pre_map.hdb
....\.........\..\top.psp
....\.........\..\top.rtlv.hdb
....\.........\..\top.rtlv_sg.cdb
....\.........\..\top.rtlv_sg_swap.cdb
....\.........\..\top.sgdiff.cdb
....\.........\..\top.sgdiff.hdb
....\.........\..\top.signalprobe.cdb
....\.........\..\top.sld_design_entry.sci
....\.........\..\top.sld_design_entry_dsc.sci
....\.........\..\top.syn_hier_info
....\.........\..\top.tan.qmsg
....\.........\..\top_cmp.qrpt
....\.........\fenpin_115200.bsf
....\.........\fenpin_115200.vhd
....\.........\fenpin_even.vhd
....\.........\sent.bsf