文件名称:IIS2BT656
介绍说明－－下载内容均来自于网络，请自行研究使用
本程序功能为将音频的IIS数据插入bt656数据中一起传输。在程序中，sdata并不从外界输入，而是由内部的一个16位的counter并串转换产生，以此来检测程序在串并转换sdata时是否有遗漏。
本程序并未经过实测，但ModelSim的仿真结果正确。-this program will function as audio data into IIS bt656 together data transmission. In the process, not from outside sdata input, but by an 16 to the counter and have a string of conversion, procedures in order to detect the change sdata series and whether there are any omissions. The procedure has not been measured, but the ModelSim simulation results correctly.
本程序并未经过实测，但ModelSim的仿真结果正确。-this program will function as audio data into IIS bt656 together data transmission. In the process, not from outside sdata input, but by an 16 to the counter and have a string of conversion, procedures in order to detect the change sdata series and whether there are any omissions. The procedure has not been measured, but the ModelSim simulation results correctly.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
IIS2BT656
.........\buffer.v
.........\final_iisbt_tb.v
.........\iisbt656.v
.........\p2sprj.cr.mti
.........\p2sprj.mpf
.........\p2sprj_tb.v
.........\p_2_s.v
.........\sim0914.cr.mti
.........\sim0914.mpf
.........\state_machine.v
.........\s_2_p.v
.........\transcript
.........\vsim.wlf
.........\wave.do
.........\work
.........\....\buffer
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\......\_primary.vhd
.........\....\final_iisbt_tb
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\iisbt656
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\parelell2serial
.........\....\...............\verilog.asm
.........\....\...............\_primary.dat
.........\....\...............\_primary.vhd
.........\....\ram_dual
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\state_machine
.........\....\.............\verilog.asm
.........\....\.............\_primary.dat
.........\....\.............\_primary.vhd
.........\....\s_2_p
.........\....\.....\verilog.asm
.........\....\.....\_primary.dat
.........\....\.....\_primary.vhd
.........\....\_info
.........\buffer.v
.........\final_iisbt_tb.v
.........\iisbt656.v
.........\p2sprj.cr.mti
.........\p2sprj.mpf
.........\p2sprj_tb.v
.........\p_2_s.v
.........\sim0914.cr.mti
.........\sim0914.mpf
.........\state_machine.v
.........\s_2_p.v
.........\transcript
.........\vsim.wlf
.........\wave.do
.........\work
.........\....\buffer
.........\....\......\verilog.asm
.........\....\......\_primary.dat
.........\....\......\_primary.vhd
.........\....\final_iisbt_tb
.........\....\..............\verilog.asm
.........\....\..............\_primary.dat
.........\....\..............\_primary.vhd
.........\....\iisbt656
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\parelell2serial
.........\....\...............\verilog.asm
.........\....\...............\_primary.dat
.........\....\...............\_primary.vhd
.........\....\ram_dual
.........\....\........\verilog.asm
.........\....\........\_primary.dat
.........\....\........\_primary.vhd
.........\....\state_machine
.........\....\.............\verilog.asm
.........\....\.............\_primary.dat
.........\....\.............\_primary.vhd
.........\....\s_2_p
.........\....\.....\verilog.asm
.........\....\.....\_primary.dat
.........\....\.....\_primary.vhd
.........\....\_info