文件名称:EXPT12_10_PHAS
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数字移相信号发生器设计，采用quartus2平台-digital phase shifting generator design platform using quartus2
相关搜索： 信号发生器
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下载文件列表
EXPT12_10_PHAS
..............\ADDER10B.VHD
..............\ADDER32B.VHD
..............\cmp_state.ini
..............\DATA
..............\....\LUT10X10.HEX
..............\....\LUT10X10.MIF
..............\db
..............\..\altsyncram_m9t.tdf
..............\..\altsyncram_qg82.tdf
..............\..\altsyncram_t5b2.tdf
..............\..\cntr_0r9.tdf
..............\..\cntr_619.tdf
..............\..\cntr_en8.tdf
..............\..\cntr_iv7.tdf
..............\..\cntr_kv8.tdf
..............\..\cntr_mk7.tdf
..............\..\cntr_pd8.tdf
..............\..\dds_vhdl.asm.qmsg
..............\..\dds_vhdl.cmp.cdb
..............\..\dds_vhdl.cmp.ddb
..............\..\dds_vhdl.cmp.hdb
..............\..\dds_vhdl.cmp.rdb
..............\..\dds_vhdl.cmp.tdb
..............\..\dds_vhdl.dat_manager.dat
..............\..\dds_vhdl.db_info
..............\..\dds_vhdl.fit.qmsg
..............\..\dds_vhdl.hier_info
..............\..\dds_vhdl.hif
..............\..\dds_vhdl.icc
..............\..\dds_vhdl.map.cdb
..............\..\dds_vhdl.map.hdb
..............\..\dds_vhdl.map.qmsg
..............\..\dds_vhdl.pre_map.hdb
..............\..\dds_vhdl.project.hdb
..............\..\dds_vhdl.rtlv.hdb
..............\..\dds_vhdl.rtlv_sg.cdb
..............\..\dds_vhdl.rtlv_sg_swap.cdb
..............\..\dds_vhdl.sgdiff.cdb
..............\..\dds_vhdl.sgdiff.hdb
..............\..\dds_vhdl.signalprobe.cdb
..............\..\dds_vhdl.sld_design_entry.sci
..............\..\dds_vhdl.sld_design_entry_dsc.sci
..............\..\dds_vhdl.syn_hier_info
..............\..\dds_vhdl.tan.qmsg
..............\..\dds_vhdl_cmp.qrpt
..............\..\decode_9ie.tdf
..............\dds_vhdl.asm.rpt
..............\DDS_VHDL.CDF
..............\dds_vhdl.done
..............\dds_vhdl.fit.eqn
..............\dds_vhdl.fit.rpt
..............\dds_vhdl.fit.summary
..............\dds_vhdl.flow.rpt
..............\dds_vhdl.map.eqn
..............\dds_vhdl.map.rpt
..............\dds_vhdl.map.summary
..............\DDS_VHDL.PIN
..............\dds_vhdl.pof
..............\DDS_VHDL.QPF
..............\DDS_VHDL.QSF
..............\DDS_VHDL.QWS
..............\DDS_VHDL.SOF
..............\dds_vhdl.tan.rpt
..............\dds_vhdl.tan.summary
..............\DDS_VHDL.VHD
..............\dds_vhdl_assignment_defaults.qdf
..............\PLL20.VHD
..............\README
..............\......\GW48使用readme.txt
..............\REG10B.VHD
..............\REG32B.VHD
..............\SIN_ROM.VHD
..............\STP1.STP
..............\ADDER10B.VHD
..............\ADDER32B.VHD
..............\cmp_state.ini
..............\DATA
..............\....\LUT10X10.HEX
..............\....\LUT10X10.MIF
..............\db
..............\..\altsyncram_m9t.tdf
..............\..\altsyncram_qg82.tdf
..............\..\altsyncram_t5b2.tdf
..............\..\cntr_0r9.tdf
..............\..\cntr_619.tdf
..............\..\cntr_en8.tdf
..............\..\cntr_iv7.tdf
..............\..\cntr_kv8.tdf
..............\..\cntr_mk7.tdf
..............\..\cntr_pd8.tdf
..............\..\dds_vhdl.asm.qmsg
..............\..\dds_vhdl.cmp.cdb
..............\..\dds_vhdl.cmp.ddb
..............\..\dds_vhdl.cmp.hdb
..............\..\dds_vhdl.cmp.rdb
..............\..\dds_vhdl.cmp.tdb
..............\..\dds_vhdl.dat_manager.dat
..............\..\dds_vhdl.db_info
..............\..\dds_vhdl.fit.qmsg
..............\..\dds_vhdl.hier_info
..............\..\dds_vhdl.hif
..............\..\dds_vhdl.icc
..............\..\dds_vhdl.map.cdb
..............\..\dds_vhdl.map.hdb
..............\..\dds_vhdl.map.qmsg
..............\..\dds_vhdl.pre_map.hdb
..............\..\dds_vhdl.project.hdb
..............\..\dds_vhdl.rtlv.hdb
..............\..\dds_vhdl.rtlv_sg.cdb
..............\..\dds_vhdl.rtlv_sg_swap.cdb
..............\..\dds_vhdl.sgdiff.cdb
..............\..\dds_vhdl.sgdiff.hdb
..............\..\dds_vhdl.signalprobe.cdb
..............\..\dds_vhdl.sld_design_entry.sci
..............\..\dds_vhdl.sld_design_entry_dsc.sci
..............\..\dds_vhdl.syn_hier_info
..............\..\dds_vhdl.tan.qmsg
..............\..\dds_vhdl_cmp.qrpt
..............\..\decode_9ie.tdf
..............\dds_vhdl.asm.rpt
..............\DDS_VHDL.CDF
..............\dds_vhdl.done
..............\dds_vhdl.fit.eqn
..............\dds_vhdl.fit.rpt
..............\dds_vhdl.fit.summary
..............\dds_vhdl.flow.rpt
..............\dds_vhdl.map.eqn
..............\dds_vhdl.map.rpt
..............\dds_vhdl.map.summary
..............\DDS_VHDL.PIN
..............\dds_vhdl.pof
..............\DDS_VHDL.QPF
..............\DDS_VHDL.QSF
..............\DDS_VHDL.QWS
..............\DDS_VHDL.SOF
..............\dds_vhdl.tan.rpt
..............\dds_vhdl.tan.summary
..............\DDS_VHDL.VHD
..............\dds_vhdl_assignment_defaults.qdf
..............\PLL20.VHD
..............\README
..............\......\GW48使用readme.txt
..............\REG10B.VHD
..............\REG32B.VHD
..............\SIN_ROM.VHD
..............\STP1.STP