文件名称:myUART
介绍说明－－下载内容均来自于网络，请自行研究使用
这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for your reference, learning together.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
myUART
......\baud_test.ant
......\baud_test.jhd
......\baud_test.tbw
......\baud_test.vhw
......\baud_test.xwv
......\baud_test.xwv_bak
......\baud_test_beh.prj
......\baud_test_bencher.prj
......\baud_test_isim_beh.exe
......\CLK_DIV.vhd
......\gg.ant
......\gg.jhd
......\gg.tbw
......\gg.vhw
......\gg.xwv
......\gg.xwv_bak
......\gg_beh.prj
......\gg_bencher.prj
......\gg_isim_beh.exe
......\isim
......\....\work
......\....\....\baud
......\....\....\....\devider.h
......\....\....\....\mingw
......\....\....\....\.....\devider.obj
......\....\....\baud_test
......\....\....\.........\mingw
......\....\....\.........\.....\testbench_arch.obj
......\....\....\.........\testbench_arch.h
......\....\....\.........\xsimtestbench_arch.cpp
......\....\....\gg
......\....\....\..\mingw
......\....\....\..\.....\testbench_arch.obj
......\....\....\..\testbench_arch.h
......\....\....\..\xsimtestbench_arch.cpp
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\sub00
......\....\....\.....\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\isim.cmd
......\isim.hdlsourcefiles
......\isim.log
......\isim.tmp_save
......\.............\_1
......\isimwavedata.xwv
......\myUART.ise
......\myUART.ise_ISE_Backup
......\pepExtractor.prj
......\RBUF.vhd
......\results.txt
......\TBUF.vhd
......\top.bgn
......\top.bld
......\top.cmd_log
......\top.drc
......\top.lso
......\top.ncd
......\top.ngc
......\top.ngd
......\top.ngr
......\top.pad
......\top.par
......\top.pcf
......\top.prj
......\top.stx
......\top.syr
......\top.twr
......\top.twx
......\top.ucf
......\top.unroutes
......\top.ut
......\top.vhd
......\top.xpi
......\top.xst
......\top_last_par.ncd
......\top_map.mrp
......\top_map.ncd
......\top_map.ngm
......\top_pad.csv
......\top_pad.txt
......\TOP_summary.html
......\xilinxsim.ini
......\xst
......\...\dump.xst
......\...\........\top.prj
......\...\........\.......\ngx
......\...\........\.......\...\notopt
......\...\........\.......\...\opt
......\...\projnav.tmp
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\baud_test.ant
......\baud_test.jhd
......\baud_test.tbw
......\baud_test.vhw
......\baud_test.xwv
......\baud_test.xwv_bak
......\baud_test_beh.prj
......\baud_test_bencher.prj
......\baud_test_isim_beh.exe
......\CLK_DIV.vhd
......\gg.ant
......\gg.jhd
......\gg.tbw
......\gg.vhw
......\gg.xwv
......\gg.xwv_bak
......\gg_beh.prj
......\gg_bencher.prj
......\gg_isim_beh.exe
......\isim
......\....\work
......\....\....\baud
......\....\....\....\devider.h
......\....\....\....\mingw
......\....\....\....\.....\devider.obj
......\....\....\baud_test
......\....\....\.........\mingw
......\....\....\.........\.....\testbench_arch.obj
......\....\....\.........\testbench_arch.h
......\....\....\.........\xsimtestbench_arch.cpp
......\....\....\gg
......\....\....\..\mingw
......\....\....\..\.....\testbench_arch.obj
......\....\....\..\testbench_arch.h
......\....\....\..\xsimtestbench_arch.cpp
......\....\....\hdllib.ref
......\....\....\hdpdeps.ref
......\....\....\sub00
......\....\....\.....\vhpl00.vho
......\....\....\.....\vhpl01.vho
......\....\....\.....\vhpl02.vho
......\....\....\.....\vhpl03.vho
......\....\....\.....\vhpl04.vho
......\....\....\.....\vhpl05.vho
......\isim.cmd
......\isim.hdlsourcefiles
......\isim.log
......\isim.tmp_save
......\.............\_1
......\isimwavedata.xwv
......\myUART.ise
......\myUART.ise_ISE_Backup
......\pepExtractor.prj
......\RBUF.vhd
......\results.txt
......\TBUF.vhd
......\top.bgn
......\top.bld
......\top.cmd_log
......\top.drc
......\top.lso
......\top.ncd
......\top.ngc
......\top.ngd
......\top.ngr
......\top.pad
......\top.par
......\top.pcf
......\top.prj
......\top.stx
......\top.syr
......\top.twr
......\top.twx
......\top.ucf
......\top.unroutes
......\top.ut
......\top.vhd
......\top.xpi
......\top.xst
......\top_last_par.ncd
......\top_map.mrp
......\top_map.ncd
......\top_map.ngm
......\top_pad.csv
......\top_pad.txt
......\TOP_summary.html
......\xilinxsim.ini
......\xst
......\...\dump.xst
......\...\........\top.prj
......\...\........\.......\ngx
......\...\........\.......\...\notopt
......\...\........\.......\...\opt
......\...\projnav.tmp
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho