基于Verilog-HDL的硬件电路的实现

9.6 脉冲高电平和低电平持续时间的测量与显示

　　9.6.1 脉冲高电平和低电平持续时间测量的工作原理

　　9.6.2 高低电平持续时间测量模块的设计与实现

　　9.6.3 改进型高低电平持续时间测量模块的设计与实现

　　9.6.4 begin声明语句的使用方法

　　9.6.5 initial语句和always语句的使用方法

　　9.6.6 时标信号发生模块的设计与实现

　　9.6.7 脉冲高低电平持续时间测量的Verilog-HDL描述

　　9.6.8 脉冲高低电平持续时间测量的硬件实现

-Verilog-HDL-based hardware circuits to achieve 9.6 high and low pulse duration measurement and 9.6.1 show the high and low pulse duration of the working principle of measuring the high-low 9.6.2 duration measurement module 9.6.3 Design and Implementation of Improved Measurement of the high-low duration of the Design and Implementation of Module 9.6.4 begin the use of declaration statements 9.6.5 initial statement and statements always use 9.6.6 beacon signal occurs when the module design and 9.6.7 to achieve the high-low pulse duration measurement of Verilog-HDL descr iption 9.6.8 high-low pulse duration measurement hardware implementation