文件名称:8051core-Verilog
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利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware descr iption language of the people to see!
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下载文件列表
8051core-Verilog
................\8051core-Verilog
................\................\Acc.v
................\................\All.v
................\................\Alu.v
................\................\alu_src1_sel.v
................\................\alu_src2_sel.v
................\................\alu_src3_sel.v
................\................\Comp.v
................\................\cy_select.v
................\................\Decoder.v
................\................\Defines.v
................\................\Divide.v
................\................\Dptr.v
................\................\ext_addr_sel.v
................\................\immediate_sel.v
................\................\IndiAddr.v
................\................\Make
................\................\Multiply.v
................\................\op_select.v
................\................\Pc.v
................\................\Port_out.v
................\................\Psw.v
................\................\Ram.v
................\................\ram_rd_sel.v
................\................\Ram_sel.v
................\................\ram_wr_sel.v
................\................\Reg1.v
................\................\Reg2.v
................\................\Reg3.v
................\................\Reg4.v
................\................\Reg5.v
................\................\Reg8.v
................\................\Reg8r.v
................\................\Rom.v
................\................\rom_addr_sel.v
................\................\Sp.v
................\................\Tb_all.v
................\................\transcript
................\................\waveperl.log
................\8051core-Verilog
................\................\Acc.v
................\................\All.v
................\................\Alu.v
................\................\alu_src1_sel.v
................\................\alu_src2_sel.v
................\................\alu_src3_sel.v
................\................\Comp.v
................\................\cy_select.v
................\................\Decoder.v
................\................\Defines.v
................\................\Divide.v
................\................\Dptr.v
................\................\ext_addr_sel.v
................\................\immediate_sel.v
................\................\IndiAddr.v
................\................\Make
................\................\Multiply.v
................\................\op_select.v
................\................\Pc.v
................\................\Port_out.v
................\................\Psw.v
................\................\Ram.v
................\................\ram_rd_sel.v
................\................\Ram_sel.v
................\................\ram_wr_sel.v
................\................\Reg1.v
................\................\Reg2.v
................\................\Reg3.v
................\................\Reg4.v
................\................\Reg5.v
................\................\Reg8.v
................\................\Reg8r.v
................\................\Rom.v
................\................\rom_addr_sel.v
................\................\Sp.v
................\................\Tb_all.v
................\................\transcript
................\................\waveperl.log