文件名称:liushuideng
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代码为verilog编写的流水等程序，已在quartuous6.0上编译仿真通过，下载入电路板已实现-Code for the Verilog flow, such as the preparation procedures, have been compiled simulation quartuous6.0 passed, downloaded into the circuit board has been achieved
(系统自动生成,下载前可以参看下载内容)
下载文件列表
liushuideng
...........\db
...........\..\liushuideng.analyze_file.qmsg
...........\..\liushuideng.cbx.xml
...........\..\liushuideng.cmp.rdb
...........\..\liushuideng.db_info
...........\..\liushuideng.eco.cdb
...........\..\liushuideng.hif
...........\..\liushuideng.map.hdb
...........\..\liushuideng.map.qmsg
...........\..\liushuideng.sld_design_entry.sci
...........\..\liushuideng.sld_design_entry_dsc.sci
...........\liushuideng.done
...........\liushuideng.flow.rpt
...........\liushuideng.map.rpt
...........\liushuideng.map.smsg
...........\liushuideng.map.summary
...........\liushuideng.qpf
...........\liushuideng.qsf
...........\liushuideng.qws
...........\liushuideng.v
...........\sopc_builder_debug_log.txt
...........\db
...........\..\liushuideng.analyze_file.qmsg
...........\..\liushuideng.cbx.xml
...........\..\liushuideng.cmp.rdb
...........\..\liushuideng.db_info
...........\..\liushuideng.eco.cdb
...........\..\liushuideng.hif
...........\..\liushuideng.map.hdb
...........\..\liushuideng.map.qmsg
...........\..\liushuideng.sld_design_entry.sci
...........\..\liushuideng.sld_design_entry_dsc.sci
...........\liushuideng.done
...........\liushuideng.flow.rpt
...........\liushuideng.map.rpt
...........\liushuideng.map.smsg
...........\liushuideng.map.summary
...........\liushuideng.qpf
...........\liushuideng.qsf
...........\liushuideng.qws
...........\liushuideng.v
...........\sopc_builder_debug_log.txt