文件名称:sin

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.41mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 112***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

正弦信号发生器

..............\Source

..............\......\dataHEX

..............\......\.......\SDATA.ASM

..............\......\.......\SDATA.BIN

..............\......\.......\SDATA.HEX

..............\......\.......\SDATA.LST

..............\......\ROM.V

..............\......\SIN_TOP.V

..............\......\sin_top_TB.v

..............\Verilog

..............\.......\cmp_state.ini

..............\.......\DAC0832.QPF

..............\.......\DAC0832.QWS

..............\.......\dataHEX

..............\.......\.......\SDATA.ASM

..............\.......\.......\SDATA.BIN

..............\.......\.......\SDATA.HEX

..............\.......\.......\SDATA.LST

..............\.......\DB

..............\.......\..\altsyncram_5sq.tdf

..............\.......\..\altsyncram_jp92.tdf

..............\.......\..\altsyncram_lp92.tdf

..............\.......\..\altsyncram_np92.tdf

..............\.......\..\altsyncram_pg91.tdf

..............\.......\..\altsyncram_rg91.tdf

..............\.......\..\altsyncram_tg91.tdf

..............\.......\..\CNTR_1A9.TDF

..............\.......\..\CNTR_3A9.TDF

..............\.......\..\CNTR_7V7.TDF

..............\.......\..\CNTR_909.TDF

..............\.......\..\CNTR_B09.TDF

..............\.......\..\CNTR_FV7.TDF

..............\.......\..\CNTR_H5A.TDF

..............\.......\..\CNTR_P5A.TDF

..............\.......\..\CNTR_U68.TDF

..............\.......\..\CNTR_V68.TDF

..............\.......\..\decode_1oa.tdf

..............\.......\..\decode_rpe.tdf

..............\.......\..\MUX_VJB.TDF

..............\.......\ROM.V

..............\.......\sin_top.asm.rpt

..............\.......\SIN_TOP.CDF

..............\.......\sin_top.done

..............\.......\sin_top.fit.eqn

..............\.......\sin_top.fit.rpt

..............\.......\sin_top.fit.summary

..............\.......\sin_top.flow.rpt

..............\.......\sin_top.map.eqn

..............\.......\sin_top.map.rpt

..............\.......\sin_top.map.summary

..............\.......\SIN_TOP.PIN

..............\.......\SIN_TOP.POF

..............\.......\SIN_TOP.QSF

..............\.......\SIN_TOP.SOF

..............\.......\sin_top.tan.rpt

..............\.......\sin_top.tan.summary

..............\.......\SIN_TOP.V

..............\.......\sin_top_description.txt

..............\.......\STP1.STP

..............\_ODELSIM

..............\........\dataHEX

..............\........\.......\SDATA.ASM

..............\........\.......\SDATA.BIN

..............\........\.......\SDATA.HEX

..............\........\.......\SDATA.LST

..............\........\ROM.V

..............\........\sin_top.cr.mti

..............\........\SIN_TOP.MPF

..............\........\SIN_TOP.V

..............\........\sin_top_TB.v

..............\........\VSIM.WLF

..............\........\WORK

..............\........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s

..............\........\....\..........................................\VERILOG.ASM

..............\........\....\..........................................\_PRIMARY.DAT

..............\........\....\..........................................\_PRIMARY.VHD

..............\........\....\@l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s

..............\........\....\....................................\VERILOG.ASM

..............\........\....\....................................\_PRIMARY.DAT

..............\........\....\....................................\_PRIMARY.VHD

..............\........\....\@l@p@m_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n

..............\........\....\....................................\VERILOG.ASM

..............\........\....\....................................\_PRIMARY.DAT

..............\........\....\....................................\_PRIMARY.VHD

..............\........\....\@m@f_pll_reg

..............\........\....\............\VERILOG.ASM

..............\........\....\............\_PRIMARY.DAT

..............\........\....\............\_PRIMARY.VHD

..............\........\....\@m@f_ram7x20_syn

..............\........\....\................\VERILOG.ASM

..............\........\....\................\_PRIMARY.DAT

..............\........\....\................\_PRIMARY.VHD

..............\..

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