文件名称:I2C_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog设计了一个简洁而实用的I2C总线控制器，对大家学习FPGA和I2C总线接口等相关方面的知识有较大的帮助。-Verilog design using a simple and practical I2C bus controller, for everyone to learn FPGA and I2C bus interface and other related knowledge has a greater help.
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FPGA
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I2C_Verilog
I2C_veril
(系统自动生成,下载前可以参看下载内容)
下载文件列表
I2C总线VHDL-Verilog+HDL源码
...........................\i2c
...........................\...\bench
...........................\...\.....\CVS
...........................\...\.....\...\Entries
...........................\...\.....\...\Repository
...........................\...\.....\...\Root
...........................\...\.....\verilog
...........................\...\.....\.......\CVS
...........................\...\.....\.......\...\Entries
...........................\...\.....\.......\...\Repository
...........................\...\.....\.......\...\Root
...........................\...\.....\.......\i2c_slave_model.v
...........................\...\.....\.......\spi_slave_model.v
...........................\...\.....\.......\tst_bench_top.v
...........................\...\.....\.......\wb_master_model.v
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\doc
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\i2c_specs.pdf
...........................\...\...\src
...........................\...\...\...\CVS
...........................\...\...\...\...\Entries
...........................\...\...\...\...\Repository
...........................\...\...\...\...\Root
...........................\...\...\...\I2C_specs.doc
...........................\...\documentation
...........................\...\.............\CVS
...........................\...\.............\...\Entries
...........................\...\.............\...\Repository
...........................\...\.............\...\Root
...........................\...\rtl
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\verilog
...........................\...\...\.......\CVS
...........................\...\...\.......\...\Entries
...........................\...\...\.......\...\Repository
...........................\...\...\.......\...\Root
...........................\...\...\.......\i2c_master_bit_ctrl.v
...........................\...\...\.......\i2c_master_byte_ctrl.v
...........................\...\...\.......\i2c_master_defines.v
...........................\...\...\.......\i2c_master_top.v
...........................\...\...\.......\timescale.v
...........................\...\...\vhdl
...........................\...\...\....\CVS
...........................\...\...\....\...\Entries
...........................\...\...\....\...\Repository
...........................\...\...\....\...\Root
...........................\...\...\....\I2C.VHD
...........................\...\...\....\i2c_master_bit_ctrl.vhd
...........................\...\...\....\i2c_master_byte_ctrl.vhd
...........................\...\...\....\i2c_master_top.vhd
...........................\...\...\....\readme
...........................\...\...\....\tst_ds1621.vhd
...........................\...\sim
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\i2c_verilog
...........................\...\...\...........\CVS
...........................\...\...\...........\...\Entries
...........................\...\...\...........\...\Repository
...........................\...\...\...........\...\Root
...........................\...\...\...........\run
...........................\...\...\...........\...\bench.vcd
...........................\...\...\...........\...\CVS
...........................\...\...\...........\...\...\Entries
...........................\...\...\...........\...\...\Repository
...........................\...\...\...........\...\...\Root
...........................\...\..
...........................\i2c
...........................\...\bench
...........................\...\.....\CVS
...........................\...\.....\...\Entries
...........................\...\.....\...\Repository
...........................\...\.....\...\Root
...........................\...\.....\verilog
...........................\...\.....\.......\CVS
...........................\...\.....\.......\...\Entries
...........................\...\.....\.......\...\Repository
...........................\...\.....\.......\...\Root
...........................\...\.....\.......\i2c_slave_model.v
...........................\...\.....\.......\spi_slave_model.v
...........................\...\.....\.......\tst_bench_top.v
...........................\...\.....\.......\wb_master_model.v
...........................\...\CVS
...........................\...\...\Entries
...........................\...\...\Repository
...........................\...\...\Root
...........................\...\doc
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\i2c_specs.pdf
...........................\...\...\src
...........................\...\...\...\CVS
...........................\...\...\...\...\Entries
...........................\...\...\...\...\Repository
...........................\...\...\...\...\Root
...........................\...\...\...\I2C_specs.doc
...........................\...\documentation
...........................\...\.............\CVS
...........................\...\.............\...\Entries
...........................\...\.............\...\Repository
...........................\...\.............\...\Root
...........................\...\rtl
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\verilog
...........................\...\...\.......\CVS
...........................\...\...\.......\...\Entries
...........................\...\...\.......\...\Repository
...........................\...\...\.......\...\Root
...........................\...\...\.......\i2c_master_bit_ctrl.v
...........................\...\...\.......\i2c_master_byte_ctrl.v
...........................\...\...\.......\i2c_master_defines.v
...........................\...\...\.......\i2c_master_top.v
...........................\...\...\.......\timescale.v
...........................\...\...\vhdl
...........................\...\...\....\CVS
...........................\...\...\....\...\Entries
...........................\...\...\....\...\Repository
...........................\...\...\....\...\Root
...........................\...\...\....\I2C.VHD
...........................\...\...\....\i2c_master_bit_ctrl.vhd
...........................\...\...\....\i2c_master_byte_ctrl.vhd
...........................\...\...\....\i2c_master_top.vhd
...........................\...\...\....\readme
...........................\...\...\....\tst_ds1621.vhd
...........................\...\sim
...........................\...\...\CVS
...........................\...\...\...\Entries
...........................\...\...\...\Repository
...........................\...\...\...\Root
...........................\...\...\i2c_verilog
...........................\...\...\...........\CVS
...........................\...\...\...........\...\Entries
...........................\...\...\...........\...\Repository
...........................\...\...\...........\...\Root
...........................\...\...\...........\run
...........................\...\...\...........\...\bench.vcd
...........................\...\...\...........\...\CVS
...........................\...\...\...........\...\...\Entries
...........................\...\...\...........\...\...\Repository
...........................\...\...\...........\...\...\Root
...........................\...\..