文件名称:i2c
介绍说明－－下载内容均来自于网络，请自行研究使用
opencores上的源码，帮大家搞下来了，希望对大家有帮助 ，-opencores the source, to help engage everyone down, and they hope to have everyone help
(系统自动生成,下载前可以参看下载内容)
下载文件列表
bench
.....\CVS
.....\...\Entries
.....\...\Repository
.....\...\Root
.....\verilog
.....\.......\CVS
.....\.......\...\Entries
.....\.......\...\Repository
.....\.......\...\Root
.....\.......\i2c_slave_model.v
.....\.......\spi_slave_model.v
.....\.......\tst_bench_top.v
.....\.......\wb_master_model.v
CVS
...\Entries
...\Repository
...\Root
doc
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\i2c_specs.pdf
...\src
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\I2C_specs.doc
documentation
.............\CVS
.............\...\Entries
.............\...\Repository
.............\...\Root
rtl
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\verilog
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\i2c_master_bit_ctrl.v
...\.......\i2c_master_byte_ctrl.v
...\.......\i2c_master_defines.v
...\.......\i2c_master_top.v
...\.......\timescale.v
...\vhdl
...\....\CVS
...\....\...\Entries
...\....\...\Repository
...\....\...\Root
...\....\I2C.VHD
...\....\i2c_master_bit_ctrl.vhd
...\....\i2c_master_byte_ctrl.vhd
...\....\i2c_master_top.vhd
...\....\readme
...\....\tst_ds1621.vhd
sim
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\i2c_verilog
...\...........\CVS
...\...........\...\Entries
...\...........\...\Repository
...\...........\...\Root
...\...........\run
...\...........\...\bench.vcd
...\...........\...\CVS
...\...........\...\...\Entries
...\...........\...\...\Repository
...\...........\...\...\Root
...\...........\...\INCA_libs
...\...........\...\.........\CVS
...\...........\...\.........\...\Entries
...\...........\...\.........\...\Repository
...\...........\...\.........\...\Root
...\...........\...\ncverilog.key
...\...........\...\ncverilog.log
...\...........\...\run
...\...........\...\waves
...\...........\...\.....\CVS
...\...........\...\.....\...\Entries
...\...........\...\.....\...\Repository
...\...........\...\.....\...\Root
software
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\drivers
........\.......\CVS
........\.......\...\Entries
........\.......\...\Repository
........\.......\...\Root
.....\CVS
.....\...\Entries
.....\...\Repository
.....\...\Root
.....\verilog
.....\.......\CVS
.....\.......\...\Entries
.....\.......\...\Repository
.....\.......\...\Root
.....\.......\i2c_slave_model.v
.....\.......\spi_slave_model.v
.....\.......\tst_bench_top.v
.....\.......\wb_master_model.v
CVS
...\Entries
...\Repository
...\Root
doc
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\i2c_specs.pdf
...\src
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\I2C_specs.doc
documentation
.............\CVS
.............\...\Entries
.............\...\Repository
.............\...\Root
rtl
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\verilog
...\.......\CVS
...\.......\...\Entries
...\.......\...\Repository
...\.......\...\Root
...\.......\i2c_master_bit_ctrl.v
...\.......\i2c_master_byte_ctrl.v
...\.......\i2c_master_defines.v
...\.......\i2c_master_top.v
...\.......\timescale.v
...\vhdl
...\....\CVS
...\....\...\Entries
...\....\...\Repository
...\....\...\Root
...\....\I2C.VHD
...\....\i2c_master_bit_ctrl.vhd
...\....\i2c_master_byte_ctrl.vhd
...\....\i2c_master_top.vhd
...\....\readme
...\....\tst_ds1621.vhd
sim
...\CVS
...\...\Entries
...\...\Repository
...\...\Root
...\i2c_verilog
...\...........\CVS
...\...........\...\Entries
...\...........\...\Repository
...\...........\...\Root
...\...........\run
...\...........\...\bench.vcd
...\...........\...\CVS
...\...........\...\...\Entries
...\...........\...\...\Repository
...\...........\...\...\Root
...\...........\...\INCA_libs
...\...........\...\.........\CVS
...\...........\...\.........\...\Entries
...\...........\...\.........\...\Repository
...\...........\...\.........\...\Root
...\...........\...\ncverilog.key
...\...........\...\ncverilog.log
...\...........\...\run
...\...........\...\waves
...\...........\...\.....\CVS
...\...........\...\.....\...\Entries
...\...........\...\.....\...\Repository
...\...........\...\.....\...\Root
software
........\CVS
........\...\Entries
........\...\Repository
........\...\Root
........\drivers
........\.......\CVS
........\.......\...\Entries
........\.......\...\Repository
........\.......\...\Root