文件名称:gate
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
(系统自动生成,下载前可以参看下载内容)
下载文件列表
gate
....\cmp_state.ini
....\db
....\..\gate.asm.qmsg
....\..\gate.cbx.xml
....\..\gate.cmp.cdb
....\..\gate.cmp.hdb
....\..\gate.cmp.rdb
....\..\gate.cmp.tdb
....\..\gate.cmp0.ddb
....\..\gate.db_info
....\..\gate.eco.cdb
....\..\gate.eda.qmsg
....\..\gate.eds_overflow
....\..\gate.fit.qmsg
....\..\gate.hier_info
....\..\gate.hif
....\..\gate.map.cdb
....\..\gate.map.hdb
....\..\gate.map.qmsg
....\..\gate.pre_map.cdb
....\..\gate.pre_map.hdb
....\..\gate.psp
....\..\gate.rtlv.hdb
....\..\gate.rtlv_sg.cdb
....\..\gate.rtlv_sg_swap.cdb
....\..\gate.sgdiff.cdb
....\..\gate.sgdiff.hdb
....\..\gate.signalprobe.cdb
....\..\gate.sim.hdb
....\..\gate.sim.qmsg
....\..\gate.sim.rdb
....\..\gate.sim.vwf
....\..\gate.sld_design_entry.sci
....\..\gate.sld_design_entry_dsc.sci
....\..\gate.syn_hier_info
....\..\gate.tan.qmsg
....\..\gate_cmp.qrpt
....\..\gate_sim.qrpt
....\flop.bsf
....\flop.v
....\g
....\.\ddd.mpf
....\.\vsim.wlf
....\.\work
....\.\....\flop_vlg_check_tst
....\.\....\..................\_primary.dat
....\.\....\..................\_primary.vhd
....\.\....\flop_vlg_sample_tst
....\.\....\...................\_primary.dat
....\.\....\...................\_primary.vhd
....\.\....\flop_vlg_vec_tst
....\.\....\................\_primary.dat
....\.\....\................\_primary.vhd
....\.\....\_info
....\.\....\_opt
....\.\....\....\work_flop_vlg_sample_tst_fast.asm
....\.\....\....\work_flop_vlg_sample_tst_fast.dt2
....\.\....\....\work__info
....\.\....\....\_deps
....\.\....\_opt1
....\.\....\.....\work_flop_vlg_check_tst_fast.asm
....\.\....\.....\work_flop_vlg_check_tst_fast.dt2
....\.\....\.....\work__info
....\.\....\.....\_deps
....\.\....\_temp
....\gate.asm.rpt
....\gate.bdf
....\gate.done
....\gate.eda.rpt
....\gate.fit.eqn
....\gate.fit.rpt
....\gate.fit.summary
....\gate.flow.rpt
....\gate.map.eqn
....\gate.map.rpt
....\gate.map.summary
....\gate.pin
....\gate.pof
....\gate.qpf
....\gate.qsf
....\gate.qws
....\gate.sim.rpt
....\gate.sof
....\gate.tan.rpt
....\gate.tan.summary
....\gate.vt
....\gate.vwf
....\quartus_nativelink_simulation.log
....\simulation
....\..........\modelsim
....\..........\........\gate.vo
....\..........\........\gate.vt
....\..........\........\gate_modelsim.xrf
....\..........\........\gate_v.sdo
....\testben.cr.mti
....\testben.mpf
....\vsim.wlf
....\Waveform1.v
....\Waveform1.vt
....\cmp_state.ini
....\db
....\..\gate.asm.qmsg
....\..\gate.cbx.xml
....\..\gate.cmp.cdb
....\..\gate.cmp.hdb
....\..\gate.cmp.rdb
....\..\gate.cmp.tdb
....\..\gate.cmp0.ddb
....\..\gate.db_info
....\..\gate.eco.cdb
....\..\gate.eda.qmsg
....\..\gate.eds_overflow
....\..\gate.fit.qmsg
....\..\gate.hier_info
....\..\gate.hif
....\..\gate.map.cdb
....\..\gate.map.hdb
....\..\gate.map.qmsg
....\..\gate.pre_map.cdb
....\..\gate.pre_map.hdb
....\..\gate.psp
....\..\gate.rtlv.hdb
....\..\gate.rtlv_sg.cdb
....\..\gate.rtlv_sg_swap.cdb
....\..\gate.sgdiff.cdb
....\..\gate.sgdiff.hdb
....\..\gate.signalprobe.cdb
....\..\gate.sim.hdb
....\..\gate.sim.qmsg
....\..\gate.sim.rdb
....\..\gate.sim.vwf
....\..\gate.sld_design_entry.sci
....\..\gate.sld_design_entry_dsc.sci
....\..\gate.syn_hier_info
....\..\gate.tan.qmsg
....\..\gate_cmp.qrpt
....\..\gate_sim.qrpt
....\flop.bsf
....\flop.v
....\g
....\.\ddd.mpf
....\.\vsim.wlf
....\.\work
....\.\....\flop_vlg_check_tst
....\.\....\..................\_primary.dat
....\.\....\..................\_primary.vhd
....\.\....\flop_vlg_sample_tst
....\.\....\...................\_primary.dat
....\.\....\...................\_primary.vhd
....\.\....\flop_vlg_vec_tst
....\.\....\................\_primary.dat
....\.\....\................\_primary.vhd
....\.\....\_info
....\.\....\_opt
....\.\....\....\work_flop_vlg_sample_tst_fast.asm
....\.\....\....\work_flop_vlg_sample_tst_fast.dt2
....\.\....\....\work__info
....\.\....\....\_deps
....\.\....\_opt1
....\.\....\.....\work_flop_vlg_check_tst_fast.asm
....\.\....\.....\work_flop_vlg_check_tst_fast.dt2
....\.\....\.....\work__info
....\.\....\.....\_deps
....\.\....\_temp
....\gate.asm.rpt
....\gate.bdf
....\gate.done
....\gate.eda.rpt
....\gate.fit.eqn
....\gate.fit.rpt
....\gate.fit.summary
....\gate.flow.rpt
....\gate.map.eqn
....\gate.map.rpt
....\gate.map.summary
....\gate.pin
....\gate.pof
....\gate.qpf
....\gate.qsf
....\gate.qws
....\gate.sim.rpt
....\gate.sof
....\gate.tan.rpt
....\gate.tan.summary
....\gate.vt
....\gate.vwf
....\quartus_nativelink_simulation.log
....\simulation
....\..........\modelsim
....\..........\........\gate.vo
....\..........\........\gate.vt
....\..........\........\gate_modelsim.xrf
....\..........\........\gate_v.sdo
....\testben.cr.mti
....\testben.mpf
....\vsim.wlf
....\Waveform1.v
....\Waveform1.vt