文件名称:display
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使用VerilogHDL语言实现硬件的开发模拟，本程序是实现数码管的模拟显示-VerilogHDL use language to achieve the development of hardware simulation, this procedure is the realization of digital control of analog display
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............\cmp_state.ini
............\db
............\..\add_sub_dph.tdf
............\..\add_sub_l0f.tdf
............\..\dled.asm.qmsg
............\..\dled.cbx.xml
............\..\dled.cmp.cdb
............\..\dled.cmp.hdb
............\..\dled.cmp.rdb
............\..\dled.cmp.tdb
............\..\dled.cmp0.ddb
............\..\dled.db_info
............\..\dled.eco.cdb
............\..\dled.eds_overflow
............\..\dled.fit.qmsg
............\..\dled.fnsim.cdb
............\..\dled.fnsim.hdb
............\..\dled.hier_info
............\..\dled.hif
............\..\dled.map.cdb
............\..\dled.map.hdb
............\..\dled.map.qmsg
............\..\dled.pre_map.cdb
............\..\dled.pre_map.hdb
............\..\dled.psp
............\..\dled.rtlv.hdb
............\..\dled.rtlv_sg.cdb
............\..\dled.rtlv_sg_swap.cdb
............\..\dled.sgdiff.cdb
............\..\dled.sgdiff.hdb
............\..\dled.sim.hdb
............\..\dled.sim.qmsg
............\..\dled.sim.rdb
............\..\dled.sim.vwf
............\..\dled.sld_design_entry.sci
............\..\dled.sld_design_entry_dsc.sci
............\..\dled.syn_hier_info
............\..\dled.tan.qmsg
............\..\dled_cmp.qrpt
............\..\dled_sim.qrpt
............\..\lpm_constant_mi3.tdf
............\dled.asm.rpt
............\dled.done
............\dled.fit.eqn
............\dled.fit.rpt
............\dled.fit.summary
............\dled.flow.rpt
............\dled.map.eqn
............\dled.map.rpt
............\dled.map.summary
............\dled.pin
............\dled.pof
............\dled.qpf
............\dled.qsf
............\dled.qws
............\dled.sim.rpt
............\dled.tan.rpt
............\dled.tan.summary
............\dled.v
............\dled.vwf
............\cmp_state.ini
............\db
............\..\add_sub_dph.tdf
............\..\add_sub_l0f.tdf
............\..\dled.asm.qmsg
............\..\dled.cbx.xml
............\..\dled.cmp.cdb
............\..\dled.cmp.hdb
............\..\dled.cmp.rdb
............\..\dled.cmp.tdb
............\..\dled.cmp0.ddb
............\..\dled.db_info
............\..\dled.eco.cdb
............\..\dled.eds_overflow
............\..\dled.fit.qmsg
............\..\dled.fnsim.cdb
............\..\dled.fnsim.hdb
............\..\dled.hier_info
............\..\dled.hif
............\..\dled.map.cdb
............\..\dled.map.hdb
............\..\dled.map.qmsg
............\..\dled.pre_map.cdb
............\..\dled.pre_map.hdb
............\..\dled.psp
............\..\dled.rtlv.hdb
............\..\dled.rtlv_sg.cdb
............\..\dled.rtlv_sg_swap.cdb
............\..\dled.sgdiff.cdb
............\..\dled.sgdiff.hdb
............\..\dled.sim.hdb
............\..\dled.sim.qmsg
............\..\dled.sim.rdb
............\..\dled.sim.vwf
............\..\dled.sld_design_entry.sci
............\..\dled.sld_design_entry_dsc.sci
............\..\dled.syn_hier_info
............\..\dled.tan.qmsg
............\..\dled_cmp.qrpt
............\..\dled_sim.qrpt
............\..\lpm_constant_mi3.tdf
............\dled.asm.rpt
............\dled.done
............\dled.fit.eqn
............\dled.fit.rpt
............\dled.fit.summary
............\dled.flow.rpt
............\dled.map.eqn
............\dled.map.rpt
............\dled.map.summary
............\dled.pin
............\dled.pof
............\dled.qpf
............\dled.qsf
............\dled.qws
............\dled.sim.rpt
............\dled.tan.rpt
............\dled.tan.summary
............\dled.v
............\dled.vwf