Opencore提供的I2C代码

.....................\i2c

.....................\...\bench

.....................\...\.....\CVS

.....................\...\.....\...\Entries

.....................\...\.....\...\Repository

.....................\...\.....\...\Root

.....................\...\.....\verilog

.....................\...\.....\.......\CVS

.....................\...\.....\.......\...\Entries

.....................\...\.....\.......\...\Repository

.....................\...\.....\.......\...\Root

.....................\...\.....\.......\i2c_slave_model.v

.....................\...\.....\.......\i2c_slave_model.v.bak

.....................\...\.....\.......\spi_slave_model.v

.....................\...\.....\.......\spi_slave_model.v.bak

.....................\...\.....\.......\tst_bench_top.v

.....................\...\.....\.......\tst_bench_top.v.bak

.....................\...\.....\.......\wb_master_model.v

.....................\...\.....\.......\wb_master_model.v.bak

.....................\...\CVS

.....................\...\...\Entries

.....................\...\...\Repository

.....................\...\...\Root

.....................\...\doc

.....................\...\...\CVS

.....................\...\...\...\Entries

.....................\...\...\...\Repository

.....................\...\...\...\Root

.....................\...\...\i2c_specs.pdf

.....................\...\...\src

.....................\...\...\...\CVS

.....................\...\...\...\...\Entries

.....................\...\...\...\...\Repository

.....................\...\...\...\...\Root

.....................\...\...\...\I2C_specs.doc

.....................\...\rtl

.....................\...\...\CVS

.....................\...\...\...\Entries

.....................\...\...\...\Repository

.....................\...\...\...\Root

.....................\...\...\verilog

.....................\...\...\.......\CVS

.....................\...\...\.......\...\Entries

.....................\...\...\.......\...\Repository

.....................\...\...\.......\...\Root

.....................\...\...\.......\i2c_master_bit_ctrl.v

.....................\...\...\.......\i2c_master_bit_ctrl.v.bak

.....................\...\...\.......\i2c_master_byte_ctrl.v

.....................\...\...\.......\i2c_master_byte_ctrl.v.bak

.....................\...\...\.......\i2c_master_defines.v

.....................\...\...\.......\i2c_master_top.v

.....................\...\...\.......\i2c_master_top.v.bak

.....................\...\...\.......\timescale.v

.....................\...\...\vhdl

.....................\...\...\....\CVS

.....................\...\...\....\...\Entries

.....................\...\...\....\...\Repository

.....................\...\...\....\...\Root

.....................\...\...\....\I2C.VHD

.....................\...\...\....\i2c_master_bit_ctrl.vhd

.....................\...\...\....\i2c_master_byte_ctrl.vhd

.....................\...\...\....\i2c_master_top.vhd

.....................\...\...\....\readme

.....................\...\...\....\tst_ds1621.vhd

.....................\...\sim

.....................\...\...\CVS

.....................\...\...\...\Entries

.....................\...\...\...\Repository

.....................\...\...\...\Root

.....................\...\...\i2c.cr.mti

.....................\...\...\i2c.mpf

.....................\...\...\i2c_verilog

.....................\...\...\...........\CVS

.....................\...\...\...........\...\Entries

.....................\...\...\...........\...\Repository

.....................\...\...\...........\...\Root

.....................\...\...\...........\run

.....................\...\...\...........\...\bench.vcd

.....................\...\...\...........\...\CVS

.....................\...\...\...........\...\...\Entries

.....................\...\...\...........\...\...\Repository

.....................\...\...\...........\...\...\Root

.....................\...\...\...........\...\INCA_libs

.....................\...\...\...........\...\.........\CVS

.....................\...\...\...........\...\.........\...\Entries

.....................\...\...\...........\...\.....