文件名称:TRL_Design_of_a_asynchronous_bit_serial_data_trans
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RTL 异步数据传送模块
用verilog HDL 语言描述
输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module.
• To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
用verilog HDL 语言描述
输入为八比特数据，执行操作后异步每比特输出。-• To create Verilog-HDL module written in the RTL style appropriate for both simulation and synthesis, for an Asynchronous Serial Data Transmitter.
• To verify the correct behaviour of the transmitter by means of simulation using a Verilog test-module.
• To automatically create a logic diagram for the Asynchronous Serial Data Transmitter, generated using a Logic Synthesis tool.
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下载文件列表
TRL Design of a asynchronous bit serial data transmitter
........................................................\test_TXSysRTL.v
........................................................\TxSysRTL.ucf
........................................................\TxSysRTL.v
........................................................\test_TXSysRTL.v
........................................................\TxSysRTL.ucf
........................................................\TxSysRTL.v