文件名称:ddrsdram_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
model\mt46v4m16.v
route\ddr_sdram.csf
.....\ddr_sdram.esf
.....\ddr_sdram.psf
.....\ddr_sdram.quartus
.....\ddr_sdram.vqm
.....\pll1.v
simulation\ddr_compile_all.v
..........\ddr_sdram_tb.v
..........\modelsim.ini
..........\readme.txt
..........\work\altclklock\verilog.psm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\ddr_command\verilog.psm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\......ntrol_interface\verilog.psm
..........\....\.....................\_primary.dat
..........\....\.....................\_primary.vhd
..........\....\....data_path\verilog.psm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\....sdram\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\........._tb\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\mt46v4m16\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\pll1\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\_info
.ource\altclklock.v
......\ddr_Command.v
......\ddr_control_interface.v
......\ddr_data_path.v
......\ddr_sdram.v
......\Params.v
......\pll1.v
.ynthesis\synplicity\ddr_data_path.srm
.........\..........\ddr_data_path.srr
.........\..........\ddr_data_path.srs
.........\..........\ddr_data_path.tlg
.........\..........\ddr_data_path.xrf
.........\..........\ddr_sdram.prj
.........\..........\ddr_sdram.sdc
.........\..........\ddr_sdram.srm
.........\..........\ddr_sdram.srr
.........\..........\ddr_sdram.srs
.........\..........\ddr_sdram.tcl
.........\..........\ddr_sdram.tlg
.........\..........\ddr_sdram.vqm
.........\..........\ddr_sdram.xrf
.........\..........\ddr_sdram_cons.tcl
.........\..........\ddr_sdram_rm.tcl
doc\ddr_sdram.pdf
simulation\work\altclklock
..........\....\ddr_command
..........\....\ddr_control_interface
..........\....\ddr_data_path
..........\....\ddr_sdram
..........\....\ddr_sdram_tb
..........\....\mt46v4m16
..........\....\pll1
..........\work
.ynthesis\synplicity
model
route
simulation
source
synthesis
doc
route\ddr_sdram.csf
.....\ddr_sdram.esf
.....\ddr_sdram.psf
.....\ddr_sdram.quartus
.....\ddr_sdram.vqm
.....\pll1.v
simulation\ddr_compile_all.v
..........\ddr_sdram_tb.v
..........\modelsim.ini
..........\readme.txt
..........\work\altclklock\verilog.psm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\ddr_command\verilog.psm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\......ntrol_interface\verilog.psm
..........\....\.....................\_primary.dat
..........\....\.....................\_primary.vhd
..........\....\....data_path\verilog.psm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\....sdram\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\........._tb\verilog.psm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\mt46v4m16\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\pll1\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\_info
.ource\altclklock.v
......\ddr_Command.v
......\ddr_control_interface.v
......\ddr_data_path.v
......\ddr_sdram.v
......\Params.v
......\pll1.v
.ynthesis\synplicity\ddr_data_path.srm
.........\..........\ddr_data_path.srr
.........\..........\ddr_data_path.srs
.........\..........\ddr_data_path.tlg
.........\..........\ddr_data_path.xrf
.........\..........\ddr_sdram.prj
.........\..........\ddr_sdram.sdc
.........\..........\ddr_sdram.srm
.........\..........\ddr_sdram.srr
.........\..........\ddr_sdram.srs
.........\..........\ddr_sdram.tcl
.........\..........\ddr_sdram.tlg
.........\..........\ddr_sdram.vqm
.........\..........\ddr_sdram.xrf
.........\..........\ddr_sdram_cons.tcl
.........\..........\ddr_sdram_rm.tcl
doc\ddr_sdram.pdf
simulation\work\altclklock
..........\....\ddr_command
..........\....\ddr_control_interface
..........\....\ddr_data_path
..........\....\ddr_sdram
..........\....\ddr_sdram_tb
..........\....\mt46v4m16
..........\....\pll1
..........\work
.ynthesis\synplicity
model
route
simulation
source
synthesis
doc