文件名称:verilog_seg7
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买的Altra公司的一款Max II EPM1270T144的电路板，其中的一个用Verilog HDL 编写的驱动数码管的程序，完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
相关搜索： epm1270t144
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下载文件列表
verilog_seg7\addcont.bsf
............\addcont.v
............\bin27seg.bsf
............\bin27seg.v
............\db\cntr_mad.tdf
............\..\verilog_seg7.asm.qmsg
............\..\verilog_seg7.asm_labs.ddb
............\..\verilog_seg7.cbx.xml
............\..\verilog_seg7.cmp.cdb
............\..\verilog_seg7.cmp.hdb
............\..\verilog_seg7.cmp.qrpt
............\..\verilog_seg7.cmp.rdb
............\..\verilog_seg7.cmp.tdb
............\..\verilog_seg7.cmp0.ddb
............\..\verilog_seg7.dbp
............\..\verilog_seg7.db_info
............\..\verilog_seg7.eco.cdb
............\..\verilog_seg7.fit.qmsg
............\..\verilog_seg7.hier_info
............\..\verilog_seg7.hif
............\..\verilog_seg7.map.cdb
............\..\verilog_seg7.map.hdb
............\..\verilog_seg7.map.qmsg
............\..\verilog_seg7.pre_map.cdb
............\..\verilog_seg7.pre_map.hdb
............\..\verilog_seg7.psp
............\..\verilog_seg7.rtlv.hdb
............\..\verilog_seg7.rtlv_sg.cdb
............\..\verilog_seg7.rtlv_sg_swap.cdb
............\..\verilog_seg7.sgdiff.cdb
............\..\verilog_seg7.sgdiff.hdb
............\..\verilog_seg7.signalprobe.cdb
............\..\verilog_seg7.sld_design_entry.sci
............\..\verilog_seg7.sld_design_entry_dsc.sci
............\..\verilog_seg7.syn_hier_info
............\..\verilog_seg7.tan.qmsg
............\lpm_counter0.bsf
............\lpm_counter0.cmp
............\lpm_counter0.vhd
............\lpm_counter0_wave0.jpg
............\lpm_counter0_waveforms.html
............\lpm_counter1.bsf
............\lpm_counter1.cmp
............\lpm_counter1.vhd
............\lpm_counter1_wave0.jpg
............\lpm_counter1_waveforms.html
............\segmain.bsf
............\segmain.v
............\setup.tcl
............\subcont.bsf
............\subcont.v
............\verilog_seg7.asm.rpt
............\verilog_seg7.bdf
............\verilog_seg7.done
............\verilog_seg7.fit.eqn
............\verilog_seg7.fit.rpt
............\verilog_seg7.fit.summary
............\verilog_seg7.flow.rpt
............\verilog_seg7.map.eqn
............\verilog_seg7.map.rpt
............\verilog_seg7.map.summary
............\verilog_seg7.pin
............\verilog_seg7.pof
............\verilog_seg7.qpf
............\verilog_seg7.qsf
............\verilog_seg7.qws
............\verilog_seg7.tan.rpt
............\verilog_seg7.tan.summary
............\db
verilog_seg7
............\addcont.v
............\bin27seg.bsf
............\bin27seg.v
............\db\cntr_mad.tdf
............\..\verilog_seg7.asm.qmsg
............\..\verilog_seg7.asm_labs.ddb
............\..\verilog_seg7.cbx.xml
............\..\verilog_seg7.cmp.cdb
............\..\verilog_seg7.cmp.hdb
............\..\verilog_seg7.cmp.qrpt
............\..\verilog_seg7.cmp.rdb
............\..\verilog_seg7.cmp.tdb
............\..\verilog_seg7.cmp0.ddb
............\..\verilog_seg7.dbp
............\..\verilog_seg7.db_info
............\..\verilog_seg7.eco.cdb
............\..\verilog_seg7.fit.qmsg
............\..\verilog_seg7.hier_info
............\..\verilog_seg7.hif
............\..\verilog_seg7.map.cdb
............\..\verilog_seg7.map.hdb
............\..\verilog_seg7.map.qmsg
............\..\verilog_seg7.pre_map.cdb
............\..\verilog_seg7.pre_map.hdb
............\..\verilog_seg7.psp
............\..\verilog_seg7.rtlv.hdb
............\..\verilog_seg7.rtlv_sg.cdb
............\..\verilog_seg7.rtlv_sg_swap.cdb
............\..\verilog_seg7.sgdiff.cdb
............\..\verilog_seg7.sgdiff.hdb
............\..\verilog_seg7.signalprobe.cdb
............\..\verilog_seg7.sld_design_entry.sci
............\..\verilog_seg7.sld_design_entry_dsc.sci
............\..\verilog_seg7.syn_hier_info
............\..\verilog_seg7.tan.qmsg
............\lpm_counter0.bsf
............\lpm_counter0.cmp
............\lpm_counter0.vhd
............\lpm_counter0_wave0.jpg
............\lpm_counter0_waveforms.html
............\lpm_counter1.bsf
............\lpm_counter1.cmp
............\lpm_counter1.vhd
............\lpm_counter1_wave0.jpg
............\lpm_counter1_waveforms.html
............\segmain.bsf
............\segmain.v
............\setup.tcl
............\subcont.bsf
............\subcont.v
............\verilog_seg7.asm.rpt
............\verilog_seg7.bdf
............\verilog_seg7.done
............\verilog_seg7.fit.eqn
............\verilog_seg7.fit.rpt
............\verilog_seg7.fit.summary
............\verilog_seg7.flow.rpt
............\verilog_seg7.map.eqn
............\verilog_seg7.map.rpt
............\verilog_seg7.map.summary
............\verilog_seg7.pin
............\verilog_seg7.pof
............\verilog_seg7.qpf
............\verilog_seg7.qsf
............\verilog_seg7.qws
............\verilog_seg7.tan.rpt
............\verilog_seg7.tan.summary
............\db
verilog_seg7