文件名称:Chapter-6
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog编写的SPI协议包括了最基本的协议和功能，并通过测试。本SPI是主。-SPI using Verilog written agreement includes the most basic protocols and functions, and passing a test. The SPI is the main.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter-6\spi_controller\bench.vcd
.........\..............\chart\Thumbs.db
.........\..............\.....\图6-11.bmp
.........\..............\.....\图6-12.bmp
.........\..............\.....\图6-13.bmp
.........\..............\.....\图6-14.bmp
.........\..............\.....\图6-17.bmp
.........\..............\.....\图6-18.bmp
.........\..............\.....\图6-19.bmp
.........\..............\.....\图6-7.bmp
.........\..............\spi_clgen.v
.........\..............\spi_controller.cr.mti
.........\..............\spi_controller.mpf
.........\..............\spi_defines.v
.........\..............\spi_shift.v
.........\..............\spi_slave_model.v
.........\..............\spi_top.v
.........\..............\tb_spi_top.v
.........\..............\timescale.v
.........\..............\transcript
.........\..............\vsim.wlf
.........\..............\wave\spi_clgen.bmp
.........\..............\....\spi_shift.bmp
.........\..............\....\spi_slave_model.bmp
.........\..............\....\spi_top.bmp
.........\..............\....\tb_spi_top.bmp
.........\..............\....\Thumbs.db
.........\..............\....\wb_master_model.bmp
.........\..............\wb_master_model.v
.........\..............\.ork\spi_clgen\verilog.asm
.........\..............\....\.........\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\....shift\verilog.asm
.........\..............\....\.........\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.....lave_model\verilog.asm
.........\..............\....\...............\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\....top\verilog.asm
.........\..............\....\.......\_primary.dat
.........\..............\....\.......\_primary.vhd
.........\..............\....\tb_spi_top\verilog.asm
.........\..............\....\..........\_primary.dat
.........\..............\....\..........\_primary.vhd
.........\..............\....\wb_master_model\verilog.asm
.........\..............\....\...............\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\_info
.........\..............\....\spi_clgen
.........\..............\....\spi_shift
.........\..............\....\spi_slave_model
.........\..............\....\spi_top
.........\..............\....\tb_spi_top
.........\..............\....\wb_master_model
.........\..............\chart
.........\..............\wave
.........\..............\work
.........\spi_controller
Chapter-6
.........\..............\chart\Thumbs.db
.........\..............\.....\图6-11.bmp
.........\..............\.....\图6-12.bmp
.........\..............\.....\图6-13.bmp
.........\..............\.....\图6-14.bmp
.........\..............\.....\图6-17.bmp
.........\..............\.....\图6-18.bmp
.........\..............\.....\图6-19.bmp
.........\..............\.....\图6-7.bmp
.........\..............\spi_clgen.v
.........\..............\spi_controller.cr.mti
.........\..............\spi_controller.mpf
.........\..............\spi_defines.v
.........\..............\spi_shift.v
.........\..............\spi_slave_model.v
.........\..............\spi_top.v
.........\..............\tb_spi_top.v
.........\..............\timescale.v
.........\..............\transcript
.........\..............\vsim.wlf
.........\..............\wave\spi_clgen.bmp
.........\..............\....\spi_shift.bmp
.........\..............\....\spi_slave_model.bmp
.........\..............\....\spi_top.bmp
.........\..............\....\tb_spi_top.bmp
.........\..............\....\Thumbs.db
.........\..............\....\wb_master_model.bmp
.........\..............\wb_master_model.v
.........\..............\.ork\spi_clgen\verilog.asm
.........\..............\....\.........\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\....shift\verilog.asm
.........\..............\....\.........\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.....lave_model\verilog.asm
.........\..............\....\...............\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\....top\verilog.asm
.........\..............\....\.......\_primary.dat
.........\..............\....\.......\_primary.vhd
.........\..............\....\tb_spi_top\verilog.asm
.........\..............\....\..........\_primary.dat
.........\..............\....\..........\_primary.vhd
.........\..............\....\wb_master_model\verilog.asm
.........\..............\....\...............\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\_info
.........\..............\....\spi_clgen
.........\..............\....\spi_shift
.........\..............\....\spi_slave_model
.........\..............\....\spi_top
.........\..............\....\tb_spi_top
.........\..............\....\wb_master_model
.........\..............\chart
.........\..............\wave
.........\..............\work
.........\spi_controller
Chapter-6