文件名称:DDSFPGA_cylone
介绍说明－－下载内容均来自于网络，请自行研究使用
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDSFPGA\creat.c
.......\512.mif
.......\DDSFPGA.qpf
.......\DDSFPGA.qsf
.......\db\DDSFPGA.db_info
.......\..\DDSFPGA.rtlv_sg_swap.cdb
.......\..\DDSFPGA.fit.qmsg
.......\..\DDSFPGA.cmp.cdb
.......\..\DDSFPGA.map.qmsg
.......\..\DDSFPGA.smp_dump.txt
.......\..\DDSFPGA.asm.qmsg
.......\..\DDSFPGA.syn_hier_info
.......\..\DDSFPGA.tan.qmsg
.......\..\DDSFPGA.sim.qmsg
.......\..\DDSFPGA.sim.hdb
.......\..\DDSFPGA.pre_map.hdb
.......\..\DDSFPGA.sim.vwf
.......\..\DDSFPGA.sim.rdb
.......\..\DDSFPGA.cbx.xml
.......\..\DDSFPGA_cmp.qrpt
.......\..\DDSFPGA.pre_map.cdb
.......\..\DDSFPGA.eds_overflow
.......\..\DDSFPGA.rtlv.hdb
.......\..\DDSFPGA.map.cdb
.......\..\DDSFPGA_sim.qrpt
.......\..\DDSFPGA.sgdiff.hdb
.......\..\DDSFPGA.eco.cdb
.......\..\DDSFPGA.map.hdb
.......\..\DDSFPGA.rtlv_sg.cdb
.......\..\DDSFPGA.sgdiff.cdb
.......\..\DDSFPGA.signalprobe.cdb
.......\..\DDSFPGA.cmp.tdb
.......\..\DDSFPGA.sld_design_entry_dsc.sci
.......\..\DDSFPGA.cmp.hdb
.......\..\DDSFPGA.cmp.rdb
.......\..\DDSFPGA.cmp0.ddb
.......\..\DDSFPGA.sld_design_entry.sci
.......\..\DDSFPGA.hif
.......\..\altsyncram_88s.tdf
.......\..\DDSFPGA.hier_info
.......\..\DDSFPGA.psp
.......\db
.......\romlookup.v
.......\romlookup_bb.v
.......\DDSFPGA.done
.......\DDSFPGA.bdf
.......\DDSFPGA.qws
.......\cmp_state.ini
.......\DDSFPGA.map.rpt
.......\DDSFPGA.flow.rpt
.......\DDSFPGA.map.summary
.......\squwave.bsf
.......\Key.bsf
.......\squwave.v.bak
.......\triawave.v.bak
.......\control.v.bak
.......\triawave.bsf
.......\creat.exe
.......\1024.mif
.......\romlookup.bsf
.......\control.bsf
.......\datachoose.bsf
.......\DDSFPGA.map.eqn
.......\DDSFPGA.fit.eqn
.......\DDSFPGA.pin
.......\DDSFPGA.fit.rpt
.......\DDSFPGA.fit.summary
.......\DDSFPGA.sof
.......\DDSFPGA.pof
.......\DDSFPGA.asm.rpt
.......\DDSFPGA.tan.summary
.......\DDSFPGA.tan.rpt
.......\DDSFPGA.vwf
.......\DDSFPGA.sim.rpt
.......\datachoose.v
.......\clock_d2.v
.......\clock_d2.bsf
.......\triawave.v
.......\squwave.v
.......\control.v
.......\key.v
DDSFPGA
.......\512.mif
.......\DDSFPGA.qpf
.......\DDSFPGA.qsf
.......\db\DDSFPGA.db_info
.......\..\DDSFPGA.rtlv_sg_swap.cdb
.......\..\DDSFPGA.fit.qmsg
.......\..\DDSFPGA.cmp.cdb
.......\..\DDSFPGA.map.qmsg
.......\..\DDSFPGA.smp_dump.txt
.......\..\DDSFPGA.asm.qmsg
.......\..\DDSFPGA.syn_hier_info
.......\..\DDSFPGA.tan.qmsg
.......\..\DDSFPGA.sim.qmsg
.......\..\DDSFPGA.sim.hdb
.......\..\DDSFPGA.pre_map.hdb
.......\..\DDSFPGA.sim.vwf
.......\..\DDSFPGA.sim.rdb
.......\..\DDSFPGA.cbx.xml
.......\..\DDSFPGA_cmp.qrpt
.......\..\DDSFPGA.pre_map.cdb
.......\..\DDSFPGA.eds_overflow
.......\..\DDSFPGA.rtlv.hdb
.......\..\DDSFPGA.map.cdb
.......\..\DDSFPGA_sim.qrpt
.......\..\DDSFPGA.sgdiff.hdb
.......\..\DDSFPGA.eco.cdb
.......\..\DDSFPGA.map.hdb
.......\..\DDSFPGA.rtlv_sg.cdb
.......\..\DDSFPGA.sgdiff.cdb
.......\..\DDSFPGA.signalprobe.cdb
.......\..\DDSFPGA.cmp.tdb
.......\..\DDSFPGA.sld_design_entry_dsc.sci
.......\..\DDSFPGA.cmp.hdb
.......\..\DDSFPGA.cmp.rdb
.......\..\DDSFPGA.cmp0.ddb
.......\..\DDSFPGA.sld_design_entry.sci
.......\..\DDSFPGA.hif
.......\..\altsyncram_88s.tdf
.......\..\DDSFPGA.hier_info
.......\..\DDSFPGA.psp
.......\db
.......\romlookup.v
.......\romlookup_bb.v
.......\DDSFPGA.done
.......\DDSFPGA.bdf
.......\DDSFPGA.qws
.......\cmp_state.ini
.......\DDSFPGA.map.rpt
.......\DDSFPGA.flow.rpt
.......\DDSFPGA.map.summary
.......\squwave.bsf
.......\Key.bsf
.......\squwave.v.bak
.......\triawave.v.bak
.......\control.v.bak
.......\triawave.bsf
.......\creat.exe
.......\1024.mif
.......\romlookup.bsf
.......\control.bsf
.......\datachoose.bsf
.......\DDSFPGA.map.eqn
.......\DDSFPGA.fit.eqn
.......\DDSFPGA.pin
.......\DDSFPGA.fit.rpt
.......\DDSFPGA.fit.summary
.......\DDSFPGA.sof
.......\DDSFPGA.pof
.......\DDSFPGA.asm.rpt
.......\DDSFPGA.tan.summary
.......\DDSFPGA.tan.rpt
.......\DDSFPGA.vwf
.......\DDSFPGA.sim.rpt
.......\datachoose.v
.......\clock_d2.v
.......\clock_d2.bsf
.......\triawave.v
.......\squwave.v
.......\control.v
.......\key.v
DDSFPGA