文件名称:sdram
介绍说明－－下载内容均来自于网络，请自行研究使用
程序说明:
本次实验控制开发板上面的SDRAM完成读写功能。
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。
part1是使用Modelsim仿真的工程
part2是在开发斑上面验证的工程
目录说明:
part1:
part1_32是4m32SDRAM的仿真工程
part1_16是4m16SDRAM的仿真工程
\model文件夹里面是仿真模型
\rtl文件夹里面是源文件
\sim文件夹里面是仿真工程
\test_bench文件夹里面是测试文件
\wave文件夹里面是仿真波形
-Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Descr iption: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
本次实验控制开发板上面的SDRAM完成读写功能。
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。
part1是使用Modelsim仿真的工程
part2是在开发斑上面验证的工程
目录说明:
part1:
part1_32是4m32SDRAM的仿真工程
part1_16是4m16SDRAM的仿真工程
\model文件夹里面是仿真模型
\rtl文件夹里面是源文件
\sim文件夹里面是仿真工程
\test_bench文件夹里面是测试文件
\wave文件夹里面是仿真波形
-Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Descr iption: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
(系统自动生成,下载前可以参看下载内容)
下载文件列表
s16_sdram\introduce.txt
.........\part1\part1_32\model\mt48lc2m32b2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc2m32b2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sd32try.cr.mti
.........\.....\........\...\sd32try.mpf
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtry.cr.mti
.........\.....\........\...\vsim.wlf
.........\.....\........\...\wave.do
.........\.....\........\...\.ork\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc2m32b2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test_tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\_info
.........\.....\........\test_bench\sdram_test_tb.v
.........\.....\........\wave\32wave.bmp
.........\.....\....2_16\model\mt48lc8m16a2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc8m16a2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtest.cr.mti
.........\.....\........\...\sdtest.mpf
.........\.....\........\...\vish_stacktrace.vstf
.........\.....\........\...\vsim.wlf
.........\.....\........\...\work\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc8m16a2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test\verilog.asm
.........\.....\........\...\....\..........\_primary.dat
.........\.....\........\...\....\..........\_primary.vhd
.........\.....\........\...\....\.........._tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\test\verilog.asm
.........\.....\........\...\....\....\_primary.dat
.........\.....\........\...\.
.........\part1\part1_32\model\mt48lc2m32b2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc2m32b2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sd32try.cr.mti
.........\.....\........\...\sd32try.mpf
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtry.cr.mti
.........\.....\........\...\vsim.wlf
.........\.....\........\...\wave.do
.........\.....\........\...\.ork\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc2m32b2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test_tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\_info
.........\.....\........\test_bench\sdram_test_tb.v
.........\.....\........\wave\32wave.bmp
.........\.....\....2_16\model\mt48lc8m16a2.v
.........\.....\........\rtl\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\sim\Command.v
.........\.....\........\...\control_interface.v
.........\.....\........\...\mt48lc8m16a2.v
.........\.....\........\...\Params.v
.........\.....\........\...\sdram_test_tb.v
.........\.....\........\...\sdr_data_path.v
.........\.....\........\...\sdr_sdram.v
.........\.....\........\...\sdtest.cr.mti
.........\.....\........\...\sdtest.mpf
.........\.....\........\...\vish_stacktrace.vstf
.........\.....\........\...\vsim.wlf
.........\.....\........\...\work\command\verilog.asm
.........\.....\........\...\....\.......\_primary.dat
.........\.....\........\...\....\.......\_primary.vhd
.........\.....\........\...\....\..ntrol_interface\verilog.asm
.........\.....\........\...\....\.................\_primary.dat
.........\.....\........\...\....\.................\_primary.vhd
.........\.....\........\...\....\mt48lc8m16a2\verilog.asm
.........\.....\........\...\....\............\_primary.dat
.........\.....\........\...\....\............\_primary.vhd
.........\.....\........\...\....\sdram_test\verilog.asm
.........\.....\........\...\....\..........\_primary.dat
.........\.....\........\...\....\..........\_primary.vhd
.........\.....\........\...\....\.........._tb\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\..._data_path\verilog.asm
.........\.....\........\...\....\.............\_primary.dat
.........\.....\........\...\....\.............\_primary.vhd
.........\.....\........\...\....\....sdram\verilog.asm
.........\.....\........\...\....\.........\_primary.dat
.........\.....\........\...\....\.........\_primary.vhd
.........\.....\........\...\....\test\verilog.asm
.........\.....\........\...\....\....\_primary.dat
.........\.....\........\...\.