文件名称:VERILOG-jpeg
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog语言在FPGA上实现JPEG图片的解码，附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VERILOG-jpeg\dct\dct.v
............\...\dctu.v
............\...\dctub.v
............\...\..._bench\bench_top.v
............\...\dct_cos_table.v
............\...\dct_mac.v
............\...\dct_syn.v
............\...\fdct.v
............\...\huffman\bench\bench_top.v
............\...\.......\.....\generic_dpram.v
............\...\.......\.....\generic_fifo_lfsr.v
............\...\.......\.....\lfsr.v
............\...\.......\.....\timescale.v
............\...\.......\huffman_dec.v
............\...\.......\huffman_enc.v
............\...\.......\huffman_tables.v
............\...\ro_cnt.v
............\...\.tl_sim\Makefile.txt
............\...\ud_cnt.v
............\...\zigzag.v
............\jpeg\bench_top\jpeg_encoder.v
............\....\jpeg_encoder.v
............\....\sim\cds.lib
............\....\...\hdl.var
............\....\...\Makefile.txt
............\qnr\attic\div.v
............\...\.....\div_us.v
............\...\.....\ro_cnt.v
............\...\.....\ud_cnt.v
............\...\bench\bench_div_top.v
............\...\.....\bench_qnr_top.v
............\...\.....\timescale.v
............\...\div_su.v
............\...\div_uu.v
............\...\jpeg_qnr.v
............\rgb2ycrcb\modelsim.ini
............\.........\rgb2ycrcb\_info
............\.........\rgb2ycrcb.mpf
............\.........\rgb2ycrcb.v
............\.........\rgb2ycrcb_testbench.v
............\.........\rgb2ycrcb_webAddress.txt
............\.........\tcl_stacktrace.txt
............\.........\transcript
............\.........\work\_info
............\.un_length_coding\attic\jpeg_rle2.v
............\.................\bench\bench.v.txt
............\.................\jpeg_rle.v
............\.................\jpeg_rle1.v
............\.................\jpeg_rzs.v
............\dct\huffman\bench
............\...\dct_bench
............\...\huffman
............\...\rtl_sim
............\jpeg\bench_top
............\....\sim
............\qnr\attic
............\...\bench
............\rgb2ycrcb\rgb2ycrcb
............\.........\work
............\.un_length_coding\attic
............\.................\bench
............\dct
............\jpeg
............\qnr
............\rgb2ycrcb
............\run_length_coding
VERILOG-jpeg
............\...\dctu.v
............\...\dctub.v
............\...\..._bench\bench_top.v
............\...\dct_cos_table.v
............\...\dct_mac.v
............\...\dct_syn.v
............\...\fdct.v
............\...\huffman\bench\bench_top.v
............\...\.......\.....\generic_dpram.v
............\...\.......\.....\generic_fifo_lfsr.v
............\...\.......\.....\lfsr.v
............\...\.......\.....\timescale.v
............\...\.......\huffman_dec.v
............\...\.......\huffman_enc.v
............\...\.......\huffman_tables.v
............\...\ro_cnt.v
............\...\.tl_sim\Makefile.txt
............\...\ud_cnt.v
............\...\zigzag.v
............\jpeg\bench_top\jpeg_encoder.v
............\....\jpeg_encoder.v
............\....\sim\cds.lib
............\....\...\hdl.var
............\....\...\Makefile.txt
............\qnr\attic\div.v
............\...\.....\div_us.v
............\...\.....\ro_cnt.v
............\...\.....\ud_cnt.v
............\...\bench\bench_div_top.v
............\...\.....\bench_qnr_top.v
............\...\.....\timescale.v
............\...\div_su.v
............\...\div_uu.v
............\...\jpeg_qnr.v
............\rgb2ycrcb\modelsim.ini
............\.........\rgb2ycrcb\_info
............\.........\rgb2ycrcb.mpf
............\.........\rgb2ycrcb.v
............\.........\rgb2ycrcb_testbench.v
............\.........\rgb2ycrcb_webAddress.txt
............\.........\tcl_stacktrace.txt
............\.........\transcript
............\.........\work\_info
............\.un_length_coding\attic\jpeg_rle2.v
............\.................\bench\bench.v.txt
............\.................\jpeg_rle.v
............\.................\jpeg_rle1.v
............\.................\jpeg_rzs.v
............\dct\huffman\bench
............\...\dct_bench
............\...\huffman
............\...\rtl_sim
............\jpeg\bench_top
............\....\sim
............\qnr\attic
............\...\bench
............\rgb2ycrcb\rgb2ycrcb
............\.........\work
............\.un_length_coding\attic
............\.................\bench
............\dct
............\jpeg
............\qnr
............\rgb2ycrcb
............\run_length_coding
VERILOG-jpeg