文件名称:xapp622
介绍说明－－下载内容均来自于网络，请自行研究使用
644 MHz SDR LVDS 发射器/接收器(verilog and doc)-644-MHz SDR LVDS Transmitter/Receiver
相关搜索： lvds
SDR
verilog
LVDS
lvds
verilog
LVDS
receiver
xilinx
VHDL
LVDS
Verilog
接收器
SDR
VHDL
xapp622
Xili
SDR
verilog
LVDS
lvds
verilog
LVDS
receiver
xilinx
VHDL
LVDS
Verilog
接收器
SDR
VHDL
xapp622
Xili
(系统自动生成,下载前可以参看下载内容)
下载文件列表
xapp622-06_10_04
................\par_v2p_left
................\............\rx_sdr_16d_4to1_left.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_left.edif
................\par_v2p_right
................\.............\rx_sdr_16d_4to1_right.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\par_v2p_xlvds
................\.............\rx_sdr_16d_4to1_left.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\trim.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\.............\xlvds_base.ucf
................\par_v2_left
................\...........\rx_sdr_16d_4to1_left.edif
................\...........\top.edif
................\...........\top.ucf
................\...........\tx_clocks.edif
................\...........\tx_sdr_16d_4to1_left.edif
................\par_v2_right
................\............\rx_sdr_16d_4to1_right.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_right.edif
................\readme.txt
................\src_vlg
................\.......\rx_sdr_16d_4to1_left.v
................\.......\rx_sdr_16d_4to1_right.v
................\.......\testbench.v
................\.......\top_left.v
................\.......\top_right.v
................\.......\top_xlvds.v
................\.......\tx_clocks.v
................\.......\tx_sdr_16d_4to1_left.v
................\.......\tx_sdr_16d_4to1_right.v
xapp622.pdf
................\par_v2p_left
................\............\rx_sdr_16d_4to1_left.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_left.edif
................\par_v2p_right
................\.............\rx_sdr_16d_4to1_right.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\par_v2p_xlvds
................\.............\rx_sdr_16d_4to1_left.edif
................\.............\top.edif
................\.............\top.ucf
................\.............\trim.ucf
................\.............\tx_clocks.edif
................\.............\tx_sdr_16d_4to1_right.edif
................\.............\xlvds_base.ucf
................\par_v2_left
................\...........\rx_sdr_16d_4to1_left.edif
................\...........\top.edif
................\...........\top.ucf
................\...........\tx_clocks.edif
................\...........\tx_sdr_16d_4to1_left.edif
................\par_v2_right
................\............\rx_sdr_16d_4to1_right.edif
................\............\top.edif
................\............\top.ucf
................\............\tx_clocks.edif
................\............\tx_sdr_16d_4to1_right.edif
................\readme.txt
................\src_vlg
................\.......\rx_sdr_16d_4to1_left.v
................\.......\rx_sdr_16d_4to1_right.v
................\.......\testbench.v
................\.......\top_left.v
................\.......\top_right.v
................\.......\top_xlvds.v
................\.......\tx_clocks.v
................\.......\tx_sdr_16d_4to1_left.v
................\.......\tx_sdr_16d_4to1_right.v
xapp622.pdf