文件名称:serial_usb
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fpga实现usb口测试 fpga/altera-usb port test fpga/altera
(系统自动生成,下载前可以参看下载内容)
下载文件列表
serial_usb
..........\db
..........\..\prev_cmp_serial_verilog.asm.qmsg
..........\..\prev_cmp_serial_verilog.fit.qmsg
..........\..\prev_cmp_serial_verilog.map.qmsg
..........\..\prev_cmp_serial_verilog.qmsg
..........\..\prev_cmp_serial_verilog.tan.qmsg
..........\..\serial_verilog.asm.qmsg
..........\..\serial_verilog.asm_labs.ddb
..........\..\serial_verilog.cbx.xml
..........\..\serial_verilog.cmp.cdb
..........\..\serial_verilog.cmp.hdb
..........\..\serial_verilog.cmp.logdb
..........\..\serial_verilog.cmp.rdb
..........\..\serial_verilog.cmp.tdb
..........\..\serial_verilog.cmp0.ddb
..........\..\serial_verilog.cmp2.ddb
..........\..\serial_verilog.dbp
..........\..\serial_verilog.db_info
..........\..\serial_verilog.eco.cdb
..........\..\serial_verilog.fit.qmsg
..........\..\serial_verilog.hier_info
..........\..\serial_verilog.hif
..........\..\serial_verilog.map.cdb
..........\..\serial_verilog.map.hdb
..........\..\serial_verilog.map.logdb
..........\..\serial_verilog.map.qmsg
..........\..\serial_verilog.pre_map.cdb
..........\..\serial_verilog.pre_map.hdb
..........\..\serial_verilog.psp
..........\..\serial_verilog.pss
..........\..\serial_verilog.rtlv.hdb
..........\..\serial_verilog.rtlv_sg.cdb
..........\..\serial_verilog.rtlv_sg_swap.cdb
..........\..\serial_verilog.sgdiff.cdb
..........\..\serial_verilog.sgdiff.hdb
..........\..\serial_verilog.signalprobe.cdb
..........\..\serial_verilog.sld_design_entry.sci
..........\..\serial_verilog.sld_design_entry_dsc.sci
..........\..\serial_verilog.syn_hier_info
..........\..\serial_verilog.tan.qmsg
..........\..\serial_verilog.tis_db_list.ddb
..........\serial.bsf
..........\serial.v
..........\serial_test.vhd
..........\serial_verilog.asm.rpt
..........\serial_verilog.bdf
..........\serial_verilog.cdf
..........\serial_verilog.done
..........\serial_verilog.dpf
..........\serial_verilog.fit.eqn
..........\serial_verilog.fit.rpt
..........\serial_verilog.fit.smsg
..........\serial_verilog.fit.summary
..........\serial_verilog.flow.rpt
..........\serial_verilog.map.eqn
..........\serial_verilog.map.rpt
..........\serial_verilog.map.smsg
..........\serial_verilog.map.summary
..........\serial_verilog.pin
..........\serial_verilog.pof
..........\serial_verilog.qpf
..........\serial_verilog.qsf
..........\serial_verilog.qws
..........\serial_verilog.sof
..........\serial_verilog.tan.rpt
..........\serial_verilog.tan.summary
..........\serial_verilog_assignment_defaults.qdf
..........\setup.tcl
..........\setup.tcl.bak
..........\db
..........\..\prev_cmp_serial_verilog.asm.qmsg
..........\..\prev_cmp_serial_verilog.fit.qmsg
..........\..\prev_cmp_serial_verilog.map.qmsg
..........\..\prev_cmp_serial_verilog.qmsg
..........\..\prev_cmp_serial_verilog.tan.qmsg
..........\..\serial_verilog.asm.qmsg
..........\..\serial_verilog.asm_labs.ddb
..........\..\serial_verilog.cbx.xml
..........\..\serial_verilog.cmp.cdb
..........\..\serial_verilog.cmp.hdb
..........\..\serial_verilog.cmp.logdb
..........\..\serial_verilog.cmp.rdb
..........\..\serial_verilog.cmp.tdb
..........\..\serial_verilog.cmp0.ddb
..........\..\serial_verilog.cmp2.ddb
..........\..\serial_verilog.dbp
..........\..\serial_verilog.db_info
..........\..\serial_verilog.eco.cdb
..........\..\serial_verilog.fit.qmsg
..........\..\serial_verilog.hier_info
..........\..\serial_verilog.hif
..........\..\serial_verilog.map.cdb
..........\..\serial_verilog.map.hdb
..........\..\serial_verilog.map.logdb
..........\..\serial_verilog.map.qmsg
..........\..\serial_verilog.pre_map.cdb
..........\..\serial_verilog.pre_map.hdb
..........\..\serial_verilog.psp
..........\..\serial_verilog.pss
..........\..\serial_verilog.rtlv.hdb
..........\..\serial_verilog.rtlv_sg.cdb
..........\..\serial_verilog.rtlv_sg_swap.cdb
..........\..\serial_verilog.sgdiff.cdb
..........\..\serial_verilog.sgdiff.hdb
..........\..\serial_verilog.signalprobe.cdb
..........\..\serial_verilog.sld_design_entry.sci
..........\..\serial_verilog.sld_design_entry_dsc.sci
..........\..\serial_verilog.syn_hier_info
..........\..\serial_verilog.tan.qmsg
..........\..\serial_verilog.tis_db_list.ddb
..........\serial.bsf
..........\serial.v
..........\serial_test.vhd
..........\serial_verilog.asm.rpt
..........\serial_verilog.bdf
..........\serial_verilog.cdf
..........\serial_verilog.done
..........\serial_verilog.dpf
..........\serial_verilog.fit.eqn
..........\serial_verilog.fit.rpt
..........\serial_verilog.fit.smsg
..........\serial_verilog.fit.summary
..........\serial_verilog.flow.rpt
..........\serial_verilog.map.eqn
..........\serial_verilog.map.rpt
..........\serial_verilog.map.smsg
..........\serial_verilog.map.summary
..........\serial_verilog.pin
..........\serial_verilog.pof
..........\serial_verilog.qpf
..........\serial_verilog.qsf
..........\serial_verilog.qws
..........\serial_verilog.sof
..........\serial_verilog.tan.rpt
..........\serial_verilog.tan.summary
..........\serial_verilog_assignment_defaults.qdf
..........\setup.tcl
..........\setup.tcl.bak