文件名称:trunk-hdlc

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 184kb
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高级链路层协议的实现,vhdl,fpga-- 8 bit parallel backend interface

- use external RX and TX clocks

- Start and end of fr a me pattern generation

- Start and end of fr a me pattern checking

- Idle pattern generation and detection (all ones)

- Idle pattern is assumed only after the end of a fr a me which is signaled by an abort signal

- Zero insertion

- Abort pattern generation and checking

- Address insertion and detection by software

- CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)

- FIFO buffers and synchronization (External)

- Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)

- Q.921, LAPB and LAPD compliant.

- For complete specifications refer to spec document




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下载文件列表

trunk

.....\CODE

.....\....\LIBS

.....\....\....\hdlc_components_pkg.vhd

.....\....\....\PCK_CRC16_D8.vhd

.....\....\MEM_PKG.VHD

.....\....\RX

.....\....\..\CORE

.....\....\..\....\flag_detect.vhd

.....\....\..\....\RxChannel.vhd

.....\....\..\....\Rxcont.vhd

.....\....\..\....\Zero_detect.vhd

.....\....\..\SCRIPTS

.....\....\..\.......\WAVE.DO

.....\....\..\TB

.....\....\..\..\Rx_tb.vhd

.....\....\SPMEM.VHD

.....\....\tools_pkg.vhd

.....\....\TOP

.....\....\...\core

.....\....\...\....\hdlc.vhd

.....\....\...\....\RxBuff.vhd

.....\....\...\....\RxFCS.vhd

.....\....\...\....\RxSync.vhd

.....\....\...\....\TxBuff.vhd

.....\....\...\....\TxFCS.vhd

.....\....\...\....\TxSync.vhd

.....\....\...\....\WB_IF.vhd

.....\....\...\scripts

.....\....\...\.......\model

.....\....\...\.......\.....\build_hdlc_top.do

.....\....\...\.......\.....\build_TxFCS_Buff.do

.....\....\...\.......\.....\wave.do

.....\....\...\.......\nc-sim

.....\....\...\.......\......\build_hdlc_top.csh

.....\....\...\.......\......\build_RxFCS_Buff.csh

.....\....\...\.......\......\build_TxFCS_Buff.csh

.....\....\...\.......\......\cds.lib

.....\....\...\.......\......\hdl.var

.....\....\...\tb

.....\....\...\..\hdlc_tb.vhd

.....\....\...\..\RxTop_tb.vhd

.....\....\...\..\TxTop_tb.vhd

.....\....\TX

.....\....\..\core

.....\....\..\....\flag_ins.vhd

.....\....\..\....\TxChannel.vhd

.....\....\..\....\TXcont.vhd

.....\....\..\....\zero_ins.vhd

.....\....\..\scripts

.....\....\..\.......\wave.do

.....\....\..\tb

.....\....\..\..\tx_tb.vhd

.....\DOCS

.....\....\hdlc_features.txt

.....\....\hdlc_project.pdf

.....\....\hdlc_project.tex

.....\....\HDLC_top.dia

.....\ETC



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