文件名称:i2c
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一个I2C总线设计,同时包括了仿真验证环境，可以同过主机从机验证该I2C设计功能-this is a i2c bus verilog design ,also including the simulation environment.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c\.init
...\.init_keil
...\1.do
...\abc
...\arg.cmd
...\clk_rst.v
...\Debussy.exeLog\compiler.log
...\..............\Debussy.exe.cmd
...\..............\Debussy.exe.cmd.bak
...\..............\debussy.rc
...\..............\ToNetlist.log
...\..............\turbo.log
...\dump.v
...\i2c.v
...\i2c_clk.v
...\i2c_rreg.v
...\i2c_slave.v
...\i2c_st.v
...\i2c_tb.v
...\i2c_tbuf.v
...\i2c_wreg.v
...\INCA_libs\.ncv.lock
...\.........\cds.lib
...\.........\hdl.var
...\.........\snap.nc\.ncv.lock
...\.........\worklib\.cdsvmod
...\.........\.......\.inca.db.154.win32
...\.........\.......\cdsinfo.tag
...\.........\.......\inca.win32.154.pak
...\Makefile
...\Makefile.bak
...\micro.v
...\ncverilog.args
...\rtl\i2c.v
...\...\i2c_clk.v
...\...\i2c_rreg.v
...\...\i2c_st.v
...\...\i2c_tbuf.v
...\...\i2c_wreg.v
...\run.bat
...\sim.log
...\.td\dump.v
...\...\system_init.v
...\...\timescale.v
...\system_init.v
...\tb\clk_rst.v
...\..\i2c_slave.v
...\..\i2c_tb.v
...\..\micro.v
...\..\testfile.f
...\testfile.f
...\timescale.v
...\wave.do
...\.ork\_info
...\INCA_libs\snap.nc
...\.........\worklib
...\sim\dsn
...\...\log
...\...\rpt
...\tb\_asic
...\Debussy.exeLog
...\gold
...\INCA_libs
...\pat
...\rtl
...\scr
...\sim
...\std
...\syn
...\tb
...\work
i2c
...\.init_keil
...\1.do
...\abc
...\arg.cmd
...\clk_rst.v
...\Debussy.exeLog\compiler.log
...\..............\Debussy.exe.cmd
...\..............\Debussy.exe.cmd.bak
...\..............\debussy.rc
...\..............\ToNetlist.log
...\..............\turbo.log
...\dump.v
...\i2c.v
...\i2c_clk.v
...\i2c_rreg.v
...\i2c_slave.v
...\i2c_st.v
...\i2c_tb.v
...\i2c_tbuf.v
...\i2c_wreg.v
...\INCA_libs\.ncv.lock
...\.........\cds.lib
...\.........\hdl.var
...\.........\snap.nc\.ncv.lock
...\.........\worklib\.cdsvmod
...\.........\.......\.inca.db.154.win32
...\.........\.......\cdsinfo.tag
...\.........\.......\inca.win32.154.pak
...\Makefile
...\Makefile.bak
...\micro.v
...\ncverilog.args
...\rtl\i2c.v
...\...\i2c_clk.v
...\...\i2c_rreg.v
...\...\i2c_st.v
...\...\i2c_tbuf.v
...\...\i2c_wreg.v
...\run.bat
...\sim.log
...\.td\dump.v
...\...\system_init.v
...\...\timescale.v
...\system_init.v
...\tb\clk_rst.v
...\..\i2c_slave.v
...\..\i2c_tb.v
...\..\micro.v
...\..\testfile.f
...\testfile.f
...\timescale.v
...\wave.do
...\.ork\_info
...\INCA_libs\snap.nc
...\.........\worklib
...\sim\dsn
...\...\log
...\...\rpt
...\tb\_asic
...\Debussy.exeLog
...\gold
...\INCA_libs
...\pat
...\rtl
...\scr
...\sim
...\std
...\syn
...\tb
...\work
i2c