文件名称:CAN_I2C_USB_yuanma
介绍说明－－下载内容均来自于网络，请自行研究使用
CAN总线，I2C，USB等的FPGA实现源码，可以利用原有代码，快速开发出自己的代码，物有所值-CAN bus, I2C, USB, etc. FPGA implementation source code, we can use the original code, and to quickly develop its own code, value for money
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下载文件列表
Chapter4 Sample\使用说明.txt
...............\I2C\I2C.dhp
...............\...\I2C.npl
...............\...\__projnav.log
...............\...\automake.log
...............\...\coregen.log
...............\...\coregen.prj
...............\...\i2c_master_bit_ctrl.cmd_log
...............\...\i2c_master_bit_ctrl.lso
...............\...\i2c_master_bit_ctrl.ngc
...............\...\i2c_master_bit_ctrl.ngr
...............\...\i2c_master_bit_ctrl.prj
...............\...\i2c_master_bit_ctrl.stx
...............\...\i2c_master_bit_ctrl.syr
...............\...\i2c_master_bit_ctrl.v
...............\...\i2c_master_bit_ctrl.v.bak
...............\...\i2c_master_bit_ctrl_vhdl.prj
...............\...\i2c_master_byte_ctrl.cmd_log
...............\...\i2c_master_byte_ctrl.lso
...............\...\i2c_master_byte_ctrl.ngc
...............\...\i2c_master_byte_ctrl.ngr
...............\...\i2c_master_byte_ctrl.prj
...............\...\i2c_master_byte_ctrl.stx
...............\...\i2c_master_byte_ctrl.syr
...............\...\i2c_master_byte_ctrl.v
...............\...\i2c_master_byte_ctrl.v.bak
...............\...\i2c_master_byte_ctrl_vhdl.prj
...............\...\i2c_master_defines.v
...............\...\i2c_master_defines.v.bak
...............\...\i2c_master_top.cmd_log
...............\...\i2c_master_top.lso
...............\...\i2c_master_top.ngc
...............\...\i2c_master_top.ngr
...............\...\i2c_master_top.prj
...............\...\i2c_master_top.stx
...............\...\i2c_master_top.syr
...............\...\i2c_master_top.v
...............\...\i2c_master_top.v.bak
...............\...\i2c_master_top_vhdl.prj
...............\...\i2c_slave_model.fdo
...............\...\i2c_slave_model.ndo
...............\...\i2c_slave_model.udo
...............\...\i2c_slave_model.v
...............\...\i2c_slave_model.v.bak
...............\...\prjname.lso
...............\...\timescale.v
...............\...\transcript
...............\...\tst_bench_top.v
...............\...\wb_master_model.v
...............\...\wb_master_model.v.bak
...............\...\xst\work\hdllib.ref
...............\...\...\....\vlg67\i2c_master_top.bin
...............\...\...\....\...5C\i2c_master_byte_ctrl.bin
...............\...\...\....\...07\i2c_master_bit_ctrl.bin
...............\...\work\_info
...............\...\....\i2c_slave_model\_primary.dat
...............\...\....\...............\_primary.vhd
...............\...\....\...............\verilog.asm
...............\...\....\glbl\_primary.dat
...............\...\....\....\_primary.vhd
...............\...\....\....\verilog.asm
...............\...\__projnav\I2C.gfl
...............\...\.........\I2C_flowplus.gfl
...............\...\.........\coregen.rsp
...............\...\.........\i2c_master_bit_ctrl.xst
...............\...\.........\i2c_master_byte_ctrl.xst
...............\...\.........\i2c_master_top.xst
...............\...\.........\runXst_tcl.rsp
...............\...\.........\xst_sprjTOstx_tcl.rsp
.......5 Sample\使用说明.txt
...............\UART\UART.npl
...............\....\UART_PACKAGE.vhd
...............\....\__projnav.log
...............\....\automake.log
...............\....\baudrate_generator.jhd
...............\....\baudrate_generator.vhd
...............\....\baudrate_generator_TB.jhd
...............\....\baudrate_generator_TB.vhd
...............\....\counter.jhd
...............\....\counter.vhd
...............\....\counter_TB.jhd
...............\....\counter_TB.vhd
...............\....\detector.jhd
...............\....\detector.vhd
...............\....\detector_TB.jhd
...............\....\detector_TB.vhd
...............\....\parity_verifier.jhd
...............\....\parity_verifier.vhd
...............\....\parity_verifier_TB.jhd
...............\....\parity_verifier_TB.vhd
...............\....\shift_register.jhd
...............\....\shift_register.vhd
...............\....\shift_register_TB.jhd
...............\....\shift_register_TB.vhd
...............\....\switch.jhd
...............\....\switch.vhd
...............\....\switch_bus.jhd
...............\....\switch_bus.vhd
...............\....\switch_bus_TB.jhd
...............\....\s
...............\I2C\I2C.dhp
...............\...\I2C.npl
...............\...\__projnav.log
...............\...\automake.log
...............\...\coregen.log
...............\...\coregen.prj
...............\...\i2c_master_bit_ctrl.cmd_log
...............\...\i2c_master_bit_ctrl.lso
...............\...\i2c_master_bit_ctrl.ngc
...............\...\i2c_master_bit_ctrl.ngr
...............\...\i2c_master_bit_ctrl.prj
...............\...\i2c_master_bit_ctrl.stx
...............\...\i2c_master_bit_ctrl.syr
...............\...\i2c_master_bit_ctrl.v
...............\...\i2c_master_bit_ctrl.v.bak
...............\...\i2c_master_bit_ctrl_vhdl.prj
...............\...\i2c_master_byte_ctrl.cmd_log
...............\...\i2c_master_byte_ctrl.lso
...............\...\i2c_master_byte_ctrl.ngc
...............\...\i2c_master_byte_ctrl.ngr
...............\...\i2c_master_byte_ctrl.prj
...............\...\i2c_master_byte_ctrl.stx
...............\...\i2c_master_byte_ctrl.syr
...............\...\i2c_master_byte_ctrl.v
...............\...\i2c_master_byte_ctrl.v.bak
...............\...\i2c_master_byte_ctrl_vhdl.prj
...............\...\i2c_master_defines.v
...............\...\i2c_master_defines.v.bak
...............\...\i2c_master_top.cmd_log
...............\...\i2c_master_top.lso
...............\...\i2c_master_top.ngc
...............\...\i2c_master_top.ngr
...............\...\i2c_master_top.prj
...............\...\i2c_master_top.stx
...............\...\i2c_master_top.syr
...............\...\i2c_master_top.v
...............\...\i2c_master_top.v.bak
...............\...\i2c_master_top_vhdl.prj
...............\...\i2c_slave_model.fdo
...............\...\i2c_slave_model.ndo
...............\...\i2c_slave_model.udo
...............\...\i2c_slave_model.v
...............\...\i2c_slave_model.v.bak
...............\...\prjname.lso
...............\...\timescale.v
...............\...\transcript
...............\...\tst_bench_top.v
...............\...\wb_master_model.v
...............\...\wb_master_model.v.bak
...............\...\xst\work\hdllib.ref
...............\...\...\....\vlg67\i2c_master_top.bin
...............\...\...\....\...5C\i2c_master_byte_ctrl.bin
...............\...\...\....\...07\i2c_master_bit_ctrl.bin
...............\...\work\_info
...............\...\....\i2c_slave_model\_primary.dat
...............\...\....\...............\_primary.vhd
...............\...\....\...............\verilog.asm
...............\...\....\glbl\_primary.dat
...............\...\....\....\_primary.vhd
...............\...\....\....\verilog.asm
...............\...\__projnav\I2C.gfl
...............\...\.........\I2C_flowplus.gfl
...............\...\.........\coregen.rsp
...............\...\.........\i2c_master_bit_ctrl.xst
...............\...\.........\i2c_master_byte_ctrl.xst
...............\...\.........\i2c_master_top.xst
...............\...\.........\runXst_tcl.rsp
...............\...\.........\xst_sprjTOstx_tcl.rsp
.......5 Sample\使用说明.txt
...............\UART\UART.npl
...............\....\UART_PACKAGE.vhd
...............\....\__projnav.log
...............\....\automake.log
...............\....\baudrate_generator.jhd
...............\....\baudrate_generator.vhd
...............\....\baudrate_generator_TB.jhd
...............\....\baudrate_generator_TB.vhd
...............\....\counter.jhd
...............\....\counter.vhd
...............\....\counter_TB.jhd
...............\....\counter_TB.vhd
...............\....\detector.jhd
...............\....\detector.vhd
...............\....\detector_TB.jhd
...............\....\detector_TB.vhd
...............\....\parity_verifier.jhd
...............\....\parity_verifier.vhd
...............\....\parity_verifier_TB.jhd
...............\....\parity_verifier_TB.vhd
...............\....\shift_register.jhd
...............\....\shift_register.vhd
...............\....\shift_register_TB.jhd
...............\....\shift_register_TB.vhd
...............\....\switch.jhd
...............\....\switch.vhd
...............\....\switch_bus.jhd
...............\....\switch_bus.vhd
...............\....\switch_bus_TB.jhd
...............\....\s