文件名称:experiment5_1
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VHDL实验5，七段数码显示译码器设计。1）用VHDL设计7段数码管显示译码电路，并在VHDL描述的测试平台下对译码器进行功能仿真，给出仿真的波形。-VHDL Lab 5, Seven-Segment Display Decoder. 1) design using VHDL 7 segment LED display decoder circuit, and the VHDL descr iption of the decoder under test platform for functional simulation, the simulation waveforms.
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下载文件列表
experiment5_1\DECL7S.vhd
.............\DECL7S.qpf
.............\DECL7S.qsf
.............\DECL7S.map.rpt
.............\DECL7S.flow.rpt
.............\DECL7S.map.summary
.............\DECL7S.pin
.............\DECL7S.fit.rpt
.............\DECL7S.fit.smsg
.............\DECL7S.fit.summary
.............\DECL7S.sof
.............\DECL7S.pof
.............\DECL7S.asm.rpt
.............\DECL7S.tan.summary
.............\DECL7S.tan.rpt
.............\DECL7S.done
.............\DECL7S.qws
.............\DECL7S.vwf
.............\DECL7S.sim.rpt
.............\DECL7S.jpg
.............\DECL7S.map.eqn
.............\DECL7S.fit.eqn
.............\cmp_state.ini
.............\DECL7S_assignment_defaults.qdf
.............\db\DECL7S.db_info
.............\..\DECL7S.sim.qmsg
.............\..\DECL7S_cmp.qrpt
.............\..\DECL7S.cmp.kpt
.............\..\DECL7S.cmp.rdb
.............\..\DECL7S.rpp.qmsg
.............\..\DECL7S.cbx.xml
.............\..\DECL7S.hif
.............\..\DECL7S.hier_info
.............\..\DECL7S.sim.hdb
.............\..\DECL7S.sim.vwf
.............\..\DECL7S.sim.rdb
.............\..\DECL7S.psp
.............\..\DECL7S.eco.cdb
.............\..\DECL7S.dbp
.............\..\DECL7S.sgate.rvd
.............\..\DECL7S.sgate_sm.rvd
.............\..\DECL7S.syn_hier_info
.............\..\DECL7S.sld_design_entry.sci
.............\..\wed.zsf
.............\..\DECL7S_sim.qrpt
.............\..\DECL7S.eds_overflow
.............\..\DECL7S.map.qmsg
.............\..\DECL7S.rtlv_sg.cdb
.............\..\DECL7S.rtlv.hdb
.............\..\DECL7S.rtlv_sg_swap.cdb
.............\..\DECL7S.pre_map.hdb
.............\..\DECL7S.pre_map.cdb
.............\..\DECL7S.map.logdb
.............\..\DECL7S.sgdiff.cdb
.............\..\DECL7S.sgdiff.hdb
.............\..\DECL7S.sld_design_entry_dsc.sci
.............\..\DECL7S.map.cdb
.............\..\DECL7S.map.hdb
.............\..\DECL7S.fit.qmsg
.............\..\DECL7S.cmp.logdb
.............\..\DECL7S.asm.qmsg
.............\..\DECL7S.tan.qmsg
.............\..\DECL7S.cmp.tdb
.............\..\DECL7S.cmp0.ddb
.............\..\DECL7S.cmp.cdb
.............\..\DECL7S.signalprobe.cdb
.............\..\DECL7S.cmp.hdb
.............\db
experiment5_1
.............\DECL7S.qpf
.............\DECL7S.qsf
.............\DECL7S.map.rpt
.............\DECL7S.flow.rpt
.............\DECL7S.map.summary
.............\DECL7S.pin
.............\DECL7S.fit.rpt
.............\DECL7S.fit.smsg
.............\DECL7S.fit.summary
.............\DECL7S.sof
.............\DECL7S.pof
.............\DECL7S.asm.rpt
.............\DECL7S.tan.summary
.............\DECL7S.tan.rpt
.............\DECL7S.done
.............\DECL7S.qws
.............\DECL7S.vwf
.............\DECL7S.sim.rpt
.............\DECL7S.jpg
.............\DECL7S.map.eqn
.............\DECL7S.fit.eqn
.............\cmp_state.ini
.............\DECL7S_assignment_defaults.qdf
.............\db\DECL7S.db_info
.............\..\DECL7S.sim.qmsg
.............\..\DECL7S_cmp.qrpt
.............\..\DECL7S.cmp.kpt
.............\..\DECL7S.cmp.rdb
.............\..\DECL7S.rpp.qmsg
.............\..\DECL7S.cbx.xml
.............\..\DECL7S.hif
.............\..\DECL7S.hier_info
.............\..\DECL7S.sim.hdb
.............\..\DECL7S.sim.vwf
.............\..\DECL7S.sim.rdb
.............\..\DECL7S.psp
.............\..\DECL7S.eco.cdb
.............\..\DECL7S.dbp
.............\..\DECL7S.sgate.rvd
.............\..\DECL7S.sgate_sm.rvd
.............\..\DECL7S.syn_hier_info
.............\..\DECL7S.sld_design_entry.sci
.............\..\wed.zsf
.............\..\DECL7S_sim.qrpt
.............\..\DECL7S.eds_overflow
.............\..\DECL7S.map.qmsg
.............\..\DECL7S.rtlv_sg.cdb
.............\..\DECL7S.rtlv.hdb
.............\..\DECL7S.rtlv_sg_swap.cdb
.............\..\DECL7S.pre_map.hdb
.............\..\DECL7S.pre_map.cdb
.............\..\DECL7S.map.logdb
.............\..\DECL7S.sgdiff.cdb
.............\..\DECL7S.sgdiff.hdb
.............\..\DECL7S.sld_design_entry_dsc.sci
.............\..\DECL7S.map.cdb
.............\..\DECL7S.map.hdb
.............\..\DECL7S.fit.qmsg
.............\..\DECL7S.cmp.logdb
.............\..\DECL7S.asm.qmsg
.............\..\DECL7S.tan.qmsg
.............\..\DECL7S.cmp.tdb
.............\..\DECL7S.cmp0.ddb
.............\..\DECL7S.cmp.cdb
.............\..\DECL7S.signalprobe.cdb
.............\..\DECL7S.cmp.hdb
.............\db
experiment5_1