文件名称:LIP4101CORE_uart
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UART Verilog sourc code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LIP4101CORE_uart\CVS\Entries
................\...\Repository
................\...\Root
................\Logical Intellectual Properity Core_1.pdf
................\run_uart.do
................\transcript
................\uart.v
................\uart_acthi1shot.v
................\uart_acthi1shot.v.bak
................\uart_actlo3shot.v
................\uart_baudgen.v
................\uart_baudgen.v.bak
................\uart_core.v
................\uart_core.v.bak
................\uart_pbif.v
................\uart_rxfifo.v
................\uart_rxfsm.v
................\uart_startbit.v
................\uart_syncactlo.v
................\uart_txfifo.v
................\uart_txfsm.v
................\WORK\uart\verilog.psm
................\....\....\_primary.dat
................\....\....\_primary.vhd
................\....\...._acthi1shot\verilog.psm
................\....\...............\_primary.dat
................\....\...............\_primary.vhd
................\....\........lo3shot\verilog.psm
................\....\...............\_primary.dat
................\....\...............\_primary.vhd
................\....\.....baudgen\verilog.psm
................\....\............\_primary.dat
................\....\............\_primary.vhd
................\....\.....core\verilog.psm
................\....\.........\_primary.dat
................\....\.........\_primary.vhd
................\....\.....pbif\verilog.psm
................\....\.........\_primary.dat
................\....\.........\_primary.vhd
................\....\.....rxfifo\verilog.psm
................\....\...........\_primary.dat
................\....\...........\_primary.vhd
................\....\........sm\verilog.psm
................\....\..........\_primary.dat
................\....\..........\_primary.vhd
................\....\.....startbit\verilog.psm
................\....\.............\_primary.dat
................\....\.............\_primary.vhd
................\....\......yncactlo\verilog.psm
................\....\..............\_primary.dat
................\....\..............\_primary.vhd
................\....\.....txfifo\verilog.psm
................\....\...........\_primary.dat
................\....\...........\_primary.vhd
................\....\........sm\verilog.psm
................\....\..........\_primary.dat
................\....\..........\_primary.vhd
................\....\_info
................\....\uart
................\....\uart_acthi1shot
................\....\uart_actlo3shot
................\....\uart_baudgen
................\....\uart_core
................\....\uart_pbif
................\....\uart_rxfifo
................\....\uart_rxfsm
................\....\uart_startbit
................\....\uart_syncactlo
................\....\uart_txfifo
................\....\uart_txfsm
................\CVS
................\WORK
LIP4101CORE_uart
................\...\Repository
................\...\Root
................\Logical Intellectual Properity Core_1.pdf
................\run_uart.do
................\transcript
................\uart.v
................\uart_acthi1shot.v
................\uart_acthi1shot.v.bak
................\uart_actlo3shot.v
................\uart_baudgen.v
................\uart_baudgen.v.bak
................\uart_core.v
................\uart_core.v.bak
................\uart_pbif.v
................\uart_rxfifo.v
................\uart_rxfsm.v
................\uart_startbit.v
................\uart_syncactlo.v
................\uart_txfifo.v
................\uart_txfsm.v
................\WORK\uart\verilog.psm
................\....\....\_primary.dat
................\....\....\_primary.vhd
................\....\...._acthi1shot\verilog.psm
................\....\...............\_primary.dat
................\....\...............\_primary.vhd
................\....\........lo3shot\verilog.psm
................\....\...............\_primary.dat
................\....\...............\_primary.vhd
................\....\.....baudgen\verilog.psm
................\....\............\_primary.dat
................\....\............\_primary.vhd
................\....\.....core\verilog.psm
................\....\.........\_primary.dat
................\....\.........\_primary.vhd
................\....\.....pbif\verilog.psm
................\....\.........\_primary.dat
................\....\.........\_primary.vhd
................\....\.....rxfifo\verilog.psm
................\....\...........\_primary.dat
................\....\...........\_primary.vhd
................\....\........sm\verilog.psm
................\....\..........\_primary.dat
................\....\..........\_primary.vhd
................\....\.....startbit\verilog.psm
................\....\.............\_primary.dat
................\....\.............\_primary.vhd
................\....\......yncactlo\verilog.psm
................\....\..............\_primary.dat
................\....\..............\_primary.vhd
................\....\.....txfifo\verilog.psm
................\....\...........\_primary.dat
................\....\...........\_primary.vhd
................\....\........sm\verilog.psm
................\....\..........\_primary.dat
................\....\..........\_primary.vhd
................\....\_info
................\....\uart
................\....\uart_acthi1shot
................\....\uart_actlo3shot
................\....\uart_baudgen
................\....\uart_core
................\....\uart_pbif
................\....\uart_rxfifo
................\....\uart_rxfsm
................\....\uart_startbit
................\....\uart_syncactlo
................\....\uart_txfifo
................\....\uart_txfsm
................\CVS
................\WORK
LIP4101CORE_uart